Manual / Guide · 2022

Supplyframe 4-Bit Processor Badge — Instruction Set in Direct Mode

Author: Supplyframe, Inc.
Year: 2022
Type: Manual / Guide

instruction set
direct mode
opcodes
4-bit processor
supplyframe

INSTRUCTION SET IN DIRECT MODE Revision 4 Nov-02-2022 Supplyframe, Inc. CODING CODE OPC MNEMONIC FLAGS OPERAND X OPCODE OPCODE 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OPERAND Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 1 ADD RX,RY V Z C 2 ADC RX,RY V Z C 3 SUB RX,RY V Z C 4 SBB RX,RY V Z C 5 OR RX,RY Z 6 AND RX,RY Z 7 XOR RX,RY Z 8 MOV RX,RY 02 INC RY Z C 03 DEC RY Z C 0 0 0 0 0 0 1 0 Y Y Y Y 0 0 0 0 0 0 1 1 Y Y Y Y 0D RRC RY Z C 0 0 0 0 1 1 0 1 Y Y Y Y Supplyframe, Inc. 2 ADD X,Y Add register Y to register X Syntax: {label} ADD Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X←X+Y Description: Add with Carry contents of the register Y to the contents of the register X and place the result in the register X. Flags aﬀected: If there is the overﬂow (if X + Y > 15), set C. Otherwise, reset C. If result = 0000 after operation, set Z. Otherwise, reset Z. If there is the underﬂow for signed representation, set V. Encoding: X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 X X X X Y Y Y Y The "0001" bits are the ADD X,Y opcode The "XXXX" bits are the contents of register X The "YYYY" bits are the contents of register Y ADD 3, 13 Example: ALU SUM 0 1 2 3 S3 S2 S0 S1 ZERO 4-BIT FULL ADDER 8-bit opcode ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND RX,RY XOR RX,RY CARRY OUT Σ Σ Σ Σ 0 C 1C 0 C 1C 0 C 1C 0 C 1C A A A A B B B DATA OUT CARRY IN B 0 FORCED “NO-CARRY” FOR ADDING WITHOUT CARRY DATA IN CP R0,N ADD R0,N INC RY DEC RY DSZ RY OR R0,N AND R0,N XOR R0,N MOV RX,RY EXR N MOV RX,N BIT RG,N B3 A3 OVER FLOW A2 B0 B1 A0 A1 A ALU OUTPUT Z C 3 STATUS MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] MOV PC,[NN] NN B ALU INPUT V MOV [XY],R0 JR B2 2 BSET RG,M 0 1 ACCUMULATOR 0 0 1 0 0 1 1 1 1 1 1 1 1 1 V Z C 3 2 1 0 BCLR RG,M BTG RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0001 = ADD 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 0 0 1 0 0 1 1 1 1 0 1 1 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 3 ADC X,Y Add with Carry register Y to register X Syntax: {label} ADC Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X ← X + Y + Carry Description: Add with Carry contents of the register Y to the contents of the register X and place the result in the register X. Flags aﬀected: If there is the overﬂow (if X + Y + Carry > 15), set C. Otherwise, reset C. If result = 0000 after operation, set Z. Otherwise, reset Z. If there is the underﬂow for signed representation, set V. Encoding: X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 X X X X Y Y Y Y The "0010" bits are the ADD X,Y opcode The "XXXX" bits are the contents of register X The "YYYY" bits are the contents of register Y ADC 8, 6 (Carry set) Example: ALU SUM 0 1 2 3 S3 S2 S0 S1 ZERO 4-BIT FULL ADDER 8-bit opcode ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND RX,RY XOR RX,RY CARRY OUT Σ Σ Σ Σ 0 C1 C 1 C 0C 1 C 0C 1 C 0C A A A A B B B DATA OUT CARRY IN B DATA IN CP R0,N ADD R0,N INC RY DEC RY DSZ RY OR R0,N B AND R0,N ALU INPUT XOR R0,N MOV RX,RY EXR N MOV RX,N BIT RG,N B3 A3 OVER FLOW A2 B0 B1 A0 A1 A ALU OUTPUT V MOV [XY],R0 Z C 3 STATUS MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] MOV PC,[NN] JR B2 NN 2 BSET RG,M 0 1 ACCUMULATOR BCLR RG,M 0 0 0 1 1 0 0 0 0 1 0 1 1 1 V Z C 3 2 1 0 BTG RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0010 = ADC 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 0 1 0 1 0 0 0 0 1 1 0 1 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 4 SUB X,Y Subtract register Y from register X Syntax: {label} SUB Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X←X-Y Description: Subtract the contents of the register Y from the contents of the register X and place the result in the register X. Flags aﬀected: If there is the underﬂow (if Y < X), reset C. Otherwise, set C. (note: Borrow is inverse C) If result = 0000 after operation, set Z. Otherwise, reset Z. If there is the underﬂow for signed representation, set V. Encoding: X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 X X X X Y Y Y Y The "0011" bits are the SUB X,Y opcode The "XXXX" bits are the contents of register X The "YYYY" bits are the contents of register Y SUB 12, 5 Example: ALU SUM 0 1 2 3 S3 S2 S0 S1 ZERO 4-BIT FULL ADDER 8-bit opcode ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND RX,RY XOR RX,RY CARRY OUT Σ Σ Σ Σ 0 C 1C 1 C 0C 1 C 0C 1 C 0C A A A A B B B DATA OUT CARRY IN B 1 BORROW IS INVERSE CARRY, SO NO-BORROW IS CARRY SET DATA IN CP R0,N ADD R0,N INC RY DEC RY DSZ RY OR R0,N B AND R0,N ALU INPUT XOR R0,N MOV RX,RY EXR N MOV RX,N BIT RG,N B3 A3 OVER FLOW A0 A1 A V Z C 3 STATUS MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] MOV PC,[NN] JR A2 NN B0 B1 INVERSE DATA FOR SUBTRACTION ALU OUTPUT MOV [XY],R0 B2 2 BSET RG,M 0 1 ACCUMULATOR 0 0 0 1 1 0 0 0 0 1 0 1 1 1 V Z C 3 2 1 0 BCLR RG,M BTG RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0011 = SUB 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 0 1 1 1 1 0 0 0 1 0 1 0 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 5 SBB X,Y Subtract register Y from register X with borrow Syntax: {label} SBB Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X ← X - Y - Carry Description: Subtract the contents of the register Y and inverse Carry ﬂag from the contents of the register X and place the result in the register X. Flags aﬀected: If there is the underﬂow (if Y < X), reset C. Otherwise, set C. (note: Borrow is inverse C) If result = 0000 after operation, set Z. Otherwise, reset Z. If there is the underﬂow for signed representation, set V. X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 X X X X Y Y Y Y Encoding: The "0100" bits are the SbB X,Y opcode The "XXXX" bits are the contents of register X The "YYYY" bits are the contents of register Y SBB 12, 5 Example: ALU SUM 0 1 2 3 S3 S2 S0 S1 ZERO 4-BIT FULL ADDER 8-bit opcode ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND RX,RY XOR RX,RY CARRY OUT Σ Σ Σ Σ 0 C1 C 1 C 0C 1 C 0C 1 C 0C A A A A B B B DATA OUT CARRY IN B DATA IN BORROW IS INVERSE CARRY CP R0,N ADD R0,N INC RY DEC RY DSZ RY OR R0,N B AND R0,N ALU INPUT XOR R0,N MOV RX,RY EXR N MOV RX,N BIT RG,N B3 A3 OVER FLOW A0 A1 A V Z C 3 STATUS MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] MOV PC,[NN] JR A2 NN B0 B1 INVERSE DATA FOR SUBTRACTION ALU OUTPUT MOV [XY],R0 B2 2 BSET RG,M 0 1 ACCUMULATOR 0 0 0 1 1 0 0 0 0 1 0 1 1 1 V Z C 3 2 1 0 BCLR RG,M BTG RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0100 = SBB 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 1 0 0 1 1 0 0 0 1 0 1 0 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 6 OR X,Y Inclusive OR registers X and Y Syntax: {label} OR Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X ← X .OR. Y Description: Compute the logical inclusive OR operation of register X and register Y and place the result into the register X. Flags aﬀected: Flag C is not aﬀected. If result = 0000 after operation, set Z. Otherwise, reset Z. X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 X X X X Y Y Y Y Encoding: OR 6, 5 Example: ALU S3 S2 S0 S1 3 8-bit opcode CP R0,N ADD R0,N 2 ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND XOR 1 0 B3 ZERO B2 A3 A2 B0 B1 A0 A1 RY DEC RY B DSZ RY ALU INPUT OR R0,N RX,RY AND R0,N RX,RY XOR R0,N EXR N BIT RG,N A ALU OUTPUT Note: Flags C and V are not aﬀected, so they are not triggered by Clock MOV RX,RY MOV RX,N V MOV [XY],R0 Z C 3 STATUS 2 0 1 BSET RG,M ACCUMULATOR BCLR RG,M MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] 0 0 0 0 1 1 0 0 0 0 0 1 1 1 V Z C 3 2 1 0 BTG MOV PC,[NN] JR INC NN RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0101 = OR 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 1 0 1 0 1 1 0 0 1 0 1 0 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 7 AND X,Y Logical AND registers X and Y Syntax: {label} AND Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X ← X .AND. Y Description: Compute the logical inclusive OR operation of register X and register Y and place the result into the register X. Flags aﬀected: Flag C is not aﬀected. If result = 0000 after operation, set Z. Otherwise, reset Z. X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 X X X X Y Y Y Y Encoding: The "0110" bits are the AND X,Y opcode The "XXXX" bits are the contents of register X The "YYYY" bits are the contents of register Y AND 9, 3 Example: ALU S3 S2 S0 S1 3 8-bit opcode CP R0,N ADD R0,N 2 ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND XOR 1 0 B3 ZERO B2 A3 A2 B0 B1 A0 A1 RY DEC RY B DSZ RY ALU INPUT OR R0,N RX,RY AND R0,N RX,RY XOR R0,N EXR N BIT RG,N A ALU OUTPUT Note: Flags C and V are not aﬀected, so they are not triggered by Clock MOV RX,RY MOV RX,N V MOV [XY],R0 Z C 3 STATUS MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] 2 0 1 BSET RG,M ACCUMULATOR 0 0 0 1 0 0 1 0 0 0 0 0 0 1 V Z C 3 BCLR RG,M BTG MOV PC,[NN] JR INC NN 2 0 1 RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0110 = AND 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 1 1 0 1 0 0 1 0 0 1 1 0 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 8 XOR X,Y Exclusive OR registers X and Y Syntax: {label} XOR Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X ← X .OR. Y Description: Compute the logical exclusive OR operation of register X and register Y and place the result into the register X. Flags aﬀected: Flag C is not aﬀected. If result = 0000 after operation, set Z. Otherwise, reset Z. X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 X X X X Y Y Y Y Encoding: The "0111" bits are the XOR X,Y opcode The "XXXX" bits are the contents of register X The "YYYY" bits are the contents of register Y XOR 12, 9 Example: ALU S3 S2 S0 S1 3 8-bit opcode CP R0,N ADD R0,N 2 ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND XOR 1 0 B3 ZERO B2 A3 A2 B0 B1 A0 A1 RY DEC RY B DSZ RY ALU INPUT OR R0,N RX,RY AND R0,N RX,RY XOR R0,N EXR N BIT RG,N A ALU OUTPUT Note: Flags C and V are not aﬀected, so they are not triggered by Clock MOV RX,RY MOV RX,N V MOV [XY],R0 Z C 3 STATUS 2 0 1 BSET RG,M ACCUMULATOR BCLR RG,M MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] 0 0 0 1 1 0 0 0 0 0 0 1 0 1 V Z C 3 BTG MOV PC,[NN] JR INC NN 2 0 1 RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER INTERNAL DATA BUS 1 3 OPCODE 0111 = XOR 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 0 1 1 1 1 1 0 0 1 0 0 1 0 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 9 MOV X,Y Move contents of register Y to register X Syntax: {label} MOV Operands: X ∈ #0...#15 Y ∈ #0...#15 Operation: X←Y Description: Move the contents of the register Y to register X. Value of the register Y is unchanged. Flags aﬀected: None. X, Y bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 X X X X Y Y Y Y Encoding: The "1000" bits are the MOV X,Y opcode The "XXXX" bits are the old contents of register X The "YYYY" bits are the contents of register Y MOV 7, 12 Example: 8-bit opcode CP R0,N ADD RX,RY ADD R0,N ADC RX,RY INC RY SUB RX,RY DEC RY SBB RX,RY DSZ RY OR RX,RY OR R0,N AND RX,RY AND R0,N XOR RX,RY XOR R0,N EXR N BIT RG,N 3 MOV RX,RY 2 0 1 REGISTER X MOV RX,N MOV [XY],R0 MOV R0,[XY] MOV [NN],R0 MOV R0,[NN] 1 1 0 0 1 1 0 0 3 2 1 0 BSET RG,M BCLR RG,M BTG MOV PC,[NN] JR NN RG,M RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 INSTRUCTION DECODER 1 3 OPCODE 1000 = MOV 2 1 0 3 OPERAND X 2 1 0 0 OPERAND Y 1 0 0 0 0 1 1 1 1 1 0 0 0 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 10 INC Y Increment the value of register Y Syntax: {label} INC Operands: Y ∈ #0...#15 Operation: Y←Y+1 Description: Add 1 to the contents of the 4-bit register Y and place the result back into the register Y. Flags aﬀected: Flag C is not aﬀected. If result = 0000 after operation, set Z. Otherwise, reset Z. Encoding: Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Y Y Y Y The "0000 0000" bits are the INC Y opcode The "YYYY" bits are the contents of register Y INC 15 Example: ALU SUM 8-bit opcode ADD S3 S2 S0 S1 4-BIT FULL ADDER RX,RY ADC RX,RY SUB RX,RY 2 SBB RX,RY 1 OR RX,RY AND RX,RY XOR RX,RY 3 Σ Σ Σ Σ 0 C1 C 0 C1C 0 C 1C 0 C1 C A A A A B 0 B3 A3 B B2 0 ZERO B A2 0 1 Note: 0001 is the ﬁxed A MOV RX,RY ALU OUTPUT Note: Flags C and V are not aﬀected MOV [XY],R0 MOV R0,[XY] V MOV [NN],R0 STATUS JR 0 0 NN INC RY DEC RY DSZ RY OR R0,N AND R0,N XOR R0,N EXR N BIT RG,N Z 0 C 3 2 BSET RG,M BCLR RG,M 0 1 ACCUMULATOR 1 1 1 1 BTG 1 MOV PC,[NN] INSTRUCTION DECODER BITS 7...4 R0,N ALU INPUT MOV RX,N MOV R0,[NN] R0,N ADD constant (+1) for INC A0 A1 0 CARRY IN B B0 DATA IN B1 0 DATA OUT CP 1 V Z 0 1 0 3 2 3 2 C 0 0 RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 0 1 RG,M INTERNAL DATA BUS 1 OPCODE 0000 0000 = INC Y 1 0 0 OPERAND Y 0 0 0 0 0 0 0 0 1 1 1 1 1 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 11 DEC Y Decrement the value of register Y Syntax: {label} DEC Operands: Y ∈ #0...#15 Operation: Y←Y-1 Description: Add -1 to the contents of the 4-bit register Y and place the result back into the register Y. Flags aﬀected: Flag C is not aﬀected. If result = 0000 after operation, set Z. Otherwise, reset Z. Encoding: Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 Y Y Y Y The "0000 0001" bits are the DEC Y opcode The "YYYY" bits are the contents of register Y DEC 9 Example: ALU SUM 8-bit opcode ADD S3 S2 S0 S1 4-BIT FULL ADDER RX,RY ADC RX,RY SUB RX,RY 2 SBB RX,RY 1 OR RX,RY AND RX,RY XOR RX,RY 3 Σ Σ Σ Σ 1 C 1C 0 C 1C 0 C 1C 0 C0 C A A A A B 0 B3 A3 B B2 1 ZERO B A2 1 Note: 1111 is -1 in 1 signed representation A0 A1 0 CARRY IN B B0 DATA IN B1 1 DATA OUT A MOV RX,RY ALU OUTPUT Note: Flags C and V are not aﬀected MOV [XY],R0 MOV R0,[XY] V MOV [NN],R0 STATUS JR 0 0 NN R0,N INC RY DEC RY DSZ RY OR R0,N AND R0,N XOR R0,N EXR N BIT RG,N Z 0 C 3 2 BSET RG,M BCLR RG,M 0 1 ACCUMULATOR 0 1 0 0 BTG 1 MOV PC,[NN] INSTRUCTION DECODER BITS 7...4 R0,N ADD ALU INPUT MOV RX,N MOV R0,[NN] CP V 0 Z 0 1 0 3 2 3 2 C 0 0 RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 0 1 RG,M INTERNAL DATA BUS 1 OPCODE 0000 0010 = DEC Y 1 0 0 OPERAND Y 0 0 0 0 0 0 1 0 1 0 0 1 1 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 12 RRC Y Rotate right through Carry the value of register Y Syntax: {label} RRC Operands: Y ∈ #0...#15 Operation: C ← Y0, Y3 ← C, Y2 ← Y3, Y1 ← Y2, Y0 ← Y1 Description: Rotate the contents of the register Y one bit to the right through Carry and place the result back in the register Y. The Carry ﬂag is shifted into the Bit 7 of register Y, and Carry is overwritten with the Bit 0 of register Y. Flags aﬀected: Flag C is not aﬀected. If result = 0000 after operation, set Z. Otherwise, reset Z. Y bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 Y Y Y Y Encoding: The "0000 0010" bits are the RRC Y opcode The "YYYY" bits are the contents of register Y RRC 6 Example: ALU 8-bit opcode ADD RX,RY ADC RX,RY SUB RX,RY SBB RX,RY OR RX,RY AND RX,RY XOR RX,RY S3 S2 S0 S1 CP R0,N ADD R0,N INC RY 2 DEC RY 1 DSZ RY OR R0,N AND R0,N XOR R0,N EXR N MOV RX,N BIT RG,N MOV [XY],R0 BSET RG,M 1 3 0 0 0 ZERO 1 1 1 1 0 0 1 CARRY CARRY A3 A2 A0 A1 A MOV RX,RY ALU OUTPUT ALU INPUT MOV R0,[XY] V MOV [NN],R0 STATUS 0 MOV R0,[NN] Z 0 C 3 2 BCLR RG,M 0 1 ACCUMULATOR 0 0 1 1 BTG 0 MOV PC,[NN] JR 0 NN INSTRUCTION DECODER BITS 7...4 V 0 Z 0 1 0 3 2 3 2 C 1 1 RRC RY RET R0,N SKIP F,M INSTRUCTION DECODER BITS 3...0 0 1 RG,M INTERNAL DATA BUS 1 OPCODE 0000 0011 = RRC Y 1 0 0 OPERAND Y 0 0 0 0 0 0 1 1 0 1 1 0 1 0 bit 11 10 9 8 7 6 5 4 3 2 1 0 CARRY CLOCK Supplyframe, Inc. 13