Manual / Guide · 2022

Supplyframe 4-Bit Processor Badge — Special Function Registers

Author: Supplyframe, Inc.
Year: 2022
Type: Manual / Guide

special function registers
data memory
registers
4-bit processor
supplyframe

SPECIAL FUNCTION REGISTERS Revision 4a Nov-03-2022 Supplyframe, Inc. Data Memory Organization General Purpose Registers Special Purpose Registers 0 1 2 3 4 5 6 7 8 9 A B C D E F 00 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 OUT IN JSR PCL PCM PCH 10 STACK 30 PAGE 40 50 al er en PAGE+1 G 60 e os rp ta Da 80 Pu 70 m Ra 90 A0 B0 C0 D0 E0 Alternate Register Set F0 Special Function Registers Supplyframe, Inc. 2 FLOATING DISPLAY WINDOW 20 Special Function Registers on Page 0 bit IOPos (WrFlags,1) = 0 bit IOPos (WrFlags,1) = 1 DEF F0 R0 R0 0000 F1 R1 R1 0000 F2 R2 R2 0000 F3 R3 R3 0000 F4 R4 R4 0000 F5 R5 R5 0000 F6 R6 R6 0000 F7 R7 R7 0000 F8 R8 R8 0000 F9 R9 R9 0000 FA Out R10 0000 FB In R11 0000 FC JSR JSR 0000 FD PCL PCL 0000 FE PCM PCM 0000 FF PCH PCH 0000 Note: Registers R0-R9 (or R0-R11) are general purpose registers Supplyframe, Inc. 3 Special Function Register SFR0A (Out) Description: 0x0A Register Out is the 4-bit latch which drives output ports, active when the WrFlag,1 bit (IOPos) is cleared. bit WRITING: INSTRUCTION 3 2 1 0 Out,3 Out,2 Out,1 Out,0 0 0 0 0 R0 MOV Out,R0 Out READING: INSTRUCTION at hard reset MOV R0,Out I/O CONNECTOR PINS OUTPUT Operation: This register is the output latch. Contents written in the register Out will appear on the connector output pins as logic levels. Note: This register is active only when the WrFlag,1 bit (IOPos) is cleared. Otherwise, this register serves as the General Purpose Register R10, and the register OutB (address 0xFA) is active. Supplyframe, Inc. 4 Special Function Register SFR0B (In) Description: 0x0B Register In is the input port register, active when the WrFlag,1 bit (IOPos) is cleared. I/O CONNECTOR PINS bit 3 2 INPUT 1 0 + Tx Rx RxTxPos (WrFlags, bit 0 may redirect these two connector pins to UART terminals Tx and Rx) READING: INSTRUCTION MOV R0,In bit 3 2 1 0 R0 Operation: This register is the input port register. Logic levels on the connector input pins are always transferred to the register In. Note: This register is active only when the WrFlag,1 (bit IOPos) is cleard. Otherwise, this register serves as the General Purpose Register R11, and the register InB (address 0xFB) is active. Note 1: When the register In is selected as the input port (when the WrFlag,1 (bit IOPos) is cleared), writing to this register is possible, but the contents will be instantly overwritten. So it makes no sense, except for dummy writes. Note 2: If the RxTxPos (WrFlags, bit 0) is set, then bit 3 of the input port (connector pin 2) is output, not input! Supplyframe, Inc. 5 Special Function Register SFR0C (JSR) Description: 0x0C Register JSR is the low-nibble address register for a subroutine call. bit WRITING: INSTRUCTION 3 2 1 0 JSR,3 JSR,2 JSR,1 JSR,0 0 0 0 0 R0 MOV JSR,R0 JSR READING: INSTRUCTION at hard reset MOV R0,JSR Operation: Reading from this register is a simple read operation, but when the program performs writing to this register, the subroutine call is automatically initiated. First, the Program Counter contents are moved to Stack, in the Data Memory addressed by the Stack register, on the three locations starting from the address 0x10+([SP]×3). After that, SP register is incremented by one, and the contents of locations JSR (low nibble), PCM and PCH (high nibble) are loaded to Program Counter. Note that only the instructions MOV RX,RY, MOV RX,N, INC RY and DEC RY will initiate the subroutine call. Modifying or writing to PCL by any other instruction will be treated as the simple memory modify or write. Note: In the following example, program calls the 2th level of subroutine from the 1st level, that's why the instruction increments SP from 1 to 2. On the next RET execution, return address 0001 1100 1011 will be reloaded back to the Program Counter, and the program will return to the level 1 of Stack Pointer. 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 ... 1011 1001 1100 0001 1011 0111 1010 1011 1100 0001 1111 0100 0 0 1 0 1 0 0001 1100 1011 PROGRAM COUNTER 1011 1001 1100 0001 1011 0111 1010 1011 1100 0001 1111 0100 0001 1100 1011 PROGRAM COUNTER Before operation Supplyframe, Inc. DATA MEMORY SP×3 JSR 0x0C PCL 0x0D PCM 0x0E PCH 0x0F STACK POINTER SP×3 DATA MEMORY STACK POINTER After operation 6 0x0C JSR 0x0D PCL 0x0E PCM 0x0F PCH 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 ... Special Function Register SFR0D (PCL) Description: 0x0D Register PCL is the low-nibble address register for a program jump. bit WRITING: INSTRUCTION 3 2 1 0 PCL,3 PCL,2 PCL,1 PCL,0 0 0 0 0 R0 MOV PCL,R0 PCL READING: INSTRUCTION at hard reset MOV R0,PCL Operation: Reading from this register is a simple read operation, but when the program performs writing to this register, the program jump is automatically initiated. The contents of locations PCL (low nibble), PCM and PCH (high nibble) are loaded to Program Counter. Note that only the instructions MOV RX,RY, MOV RX,N, INC RY and DEC RY will initiate the program jump. Modifying or writing to PCL by any other instruction will be treated as the simple memory modify or write. Note: In the following example, program jumps from the address 0001 0011 1100 (Program Counter always points to the next address) to the location 0001 0011 1101, determined by registers PCH (high nibble), PCM and PCL (low nibble). Only Program Counter is modiﬁed, the contents of all other registers are unaﬀected. DATA MEMORY DATA MEMORY 0100 1101 0011 0001 0100 1101 0011 0001 JSR 0x0C PCL 0x0D PCM 0x0E PCH 0x0F 0x10 0000 1111 0001 PROGRAM COUNTER 0001 0011 1101 PROGRAM COUNTER Before operation Supplyframe, Inc. After operation 7 0x0C JSR 0x0D PCL 0x0E PCM 0x0F PCH 0x10 Special Function Register SFR0E (PCM) Description: 0x0E Register PCM is the next-nibble address register for program jump or subroutine call. bit WRITING: INSTRUCTION 3 2 1 0 PCM,3 PCM,2 PCM,1 PCM,0 0 0 0 0 R0 MOV PCM,R0 PCM READING: INSTRUCTION at hard reset MOV R0,PCM Operation: Reading from or writing to this register is a simple read or write operation, so it does not aﬀect the program ﬂow. However, this register will take action when program jump (writing to PCL) or subroutine call (writing to JSR) occurs, as it will be a part of the Program Counter contents. The following example shows how PCM aﬀects the ﬁnal Program Counter contents during the program jump. The eﬀect is similar in Subroutine Call, only the lower nibble of the Program Counter is not loaded from PCL, but from JSR. DATA MEMORY DATA MEMORY 0100 1101 0011 0001 0100 1101 0011 0001 JSR 0x0C PCL 0x0D PCM 0x0E PCH 0x0F 0x10 0000 1111 0001 PROGRAM COUNTER 0001 0011 1101 PROGRAM COUNTER Before operation Supplyframe, Inc. After operation 8 0x0C JSR 0x0D PCL 0x0E PCM 0x0F PCH 0x10 Special Function Register SFR0F (PCH) Description: 0x0F Register PCH is the next-nibble address register for program jump or subroutine call. bit WRITING: INSTRUCTION 3 2 1 0 PCH,3 PCH,2 PCH,1 PCH,0 0 0 0 0 R0 MOV PCH,R0 PCH READING: INSTRUCTION at hard reset MOV R0,PCH Operation: Reading from or writing to this register is a simple read or write operation, so it does not aﬀect the program ﬂow. However, this register will take action when program jump (writing to PCL) or subroutine call (writing to JSR) occurs, as it will be a part of the Program Counter contents. The following example shows how PCH aﬀects the ﬁnal Program Counter contents during the program jump. The eﬀect is similar in Subroutine Call, only the lower nibble of the Program Counter is not loaded from PCL, but from JSR. DATA MEMORY DATA MEMORY 0100 1101 0011 0001 0100 1101 0011 0001 JSR 0x0C PCL 0x0D PCM 0x0E PCH 0x0F 0x10 0000 1111 0001 PROGRAM COUNTER 0001 0011 1101 PROGRAM COUNTER Before operation Supplyframe, Inc. After operation 9 0x0C JSR 0x0D PCL 0x0E PCM 0x0F PCH 0x10 Special Function Registers on Page 15 NAME bit 3 bit 2 bit 1 bit 0 DEF F0 Page PAGE 0000 F1 Clock CLOCK 0000 F2 Sync SYNC 0000 F3 WrFlags LedsOﬀ F4 RdFlags Reserved Reserved F5 SerCtrl RxError F6 SerLow SER LOW 0000 F7 SerHigh SER HIGH 0000 F8 Received RECEIVED 0000 F9 AutoOﬀ AUTO OFF 0010 FA OutB OUT B 0000 FB InB IN B 0000 FC KeyStatus AltPress MatrixOﬀ InOutPos Vﬂag BaudRate RxTxPos 0000 UserSync 0000 0011 AnyPress LastPress JustPress 0000 FD KeyReg KEY REG 0000 FE Dimmer DIMMER 0000 FF Random RANDOM 0000 Note: Bits with Flag symbol are automatically cleared after register reading Supplyframe, Inc. 10 Special Function Register SFRF0 (Page) Description: 0xF0 Register Page selects which pages from the data memory will be dipslayed. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV Page,R0 READING: INSTRUCTION Page Page,3 Page,2 Page,1 Page,0 0 0 0 0 DEFAULT at every program RUN and stop MOV R0,Page Operation: LED matrix with the resolution 8×16 displays two pages of data memory, 16 nibbles each. Register Page selects which page will be displayed. Selected page is on the right halve of the display, with the ﬁrst nibble (address xxxx 0000) at the top, and the last one (xxxx 1111) at the bottom. Bit 3 is in the left column, and the bit 0 in the right. The next page is displayed on the left halve, with the same order. Special case: If the selected page is 15 (which is the last page), the Next Page (displayed on the left halve of the matrix) will be page 0. This can be used to watch the main register set (Page 0) and the SFR set (Page 15) at the same time. Note: Contents of SFR register Page can be easily modiﬁed by holding button ALT and using buttons in Operand Y ﬁeld to select the value. While button ALT is depressed, only Page 0 is displayed (which can be used to see the main register set on Page 0 promptly), but when the button ALT is released, the matrix will display the selected page. Bit 3 2 1 0 3 2 1 0 Address (Page+1) × 16 Address Page × 16 Page Page+1 Address (Page+1) × 16 + 15 Supplyframe, Inc. Address Page × 16 + 15 11 Special Function Register SFRF1 (Clock) Description: 0xF1 Register Clock selects one of 16 available processor speeds. bit WRITING: INSTRUCTION 3 2 1 0 Clock,3 Clock,2 Clock,1 Clock,0 0 0 0 0 R0 MOV Clock,R0 READING: INSTRUCTION Clock DEFAULT at every program RUN MOV R0,Clock SYSTEM CLOCK 0 1 2 3 4 5 6 7 8 9 DIVIDER SIMULATED CLOCK 11 12 13 14 15 Operation: All functions of the hypothetical processor are simulated by the 16-bit microcontroller PIC24FJ256GA704-I/PT, running at 16 MHz. As every instruction needs to be executed by a group of the microcontroller instructions, the maximum execution speed is not constant and it greatly depends on the instructions used in the user’s program. SFR1 Frequency Period 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ~250 KHz 100 KHz 30 KHz 10 KHz 3 KHz 1 KHz 500 Hz 200 Hz 100 Hz 50 Hz 20 Hz 10 Hz 5 Hz 2 Hz 1 Hz 0.5 Hz ~4 µs ~10 µs 33 µs 100 µs 333 µs 1 ms 2 ms 5 ms 10 ms 20 ms 50 ms 100 ms 200 ms 500 ms 1 s 2 s Supplyframe, Inc. Here is the table of available frequencies and periods. After every instruction, the execution is waiting for the synchronisation with the selected output of the divider chain, except when Clock=0. In that case, the execution is the fastest possible, which is about 0.25 MIPS (about 4 µs for an average instruction). Note 1: Contents of SFR register Clock can be easily modiﬁed by holding button ALT and using buttons in Operand X ﬁeld to select the value. Note 2: On every RUN command, Clock parameter is initialized to 0000 (250 KHz). Note 3: In SS mode, Clock has no eﬀect, but it is internally initialized to 0001 for internal program reasons. 12 Special Function Register SFRF2 (Sync) Description: 0xF2 Register Sync selects one of 16 ﬁxed timings used in the frequency divider which sets the special UserSync ﬂag in the register RdFlags. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV Sync,R0 READING: INSTRUCTION Sync Sync,3 Sync,2 Sync,1 Sync,0 0 0 0 0 at hard reset MOV R0,Sync 0 1 2 3 4 5 6 f FREQUENCY DIVIDER bit RdFlags,0 SET OUT Q RESET 8 9 10 11 12 13 14 15 Internal data bus READ RdFlags Operation: Uniform clock is divided by the factor determined by the register Sync and the overﬂow pulse sets the bit #0 (UserSync) in the register RdFlags. Program can read the bit #0 in the register RdFlags (using instruction MOV R0,RdFlags) and thus synchronize the program ﬂow with the real-time ticking. Reading from register RdFlags automatically resets bit 0 (UserSync). Here is the table of available frequencies and periods: Sync Frequency Period 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1000 Hz 600 Hz 400 Hz 250 Hz 150 Hz 100 Hz 60 Hz 40 Hz 25 Hz 15 Hz 10 Hz 6 Hz 4 Hz 2.5 Hz 1.5 Hz 1 Hz 1 ms 1.67 ms 2.5 ms 4 ms 6.67 ms 10 ms 16.7 ms 25 ms 40 ms 66.7 ms 100 ms 167 ms 250 ms 400 ms 667 ms 1 sec Supplyframe, Inc. Program example: ; initialization (only once) MOV MOV R0,12 [252],R0 ; 250 ms period ; write to reg Sync MOV BIT SKIP BRA R0,[244] R0,0 3,1 -4 ; get status ; test User Sync bit ; if NZ, skip 1 line ; loop ADD R3,R6 ; program goes on... ; if this is the part of the other loop, ; program will wait here every time for ; synchronization on 250 ms, and then ; continue execution. 13 Special Function Register SFRF3 (WrFlags) Description: 0xF3 Register WrFlags contains individual control ﬂags. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV WrFlags,R0 WrFlags,3 WrFlags,2 WrFlags,1 WrFlags,0 0 0 0 0 WrFlags READING: INSTRUCTION LedsOﬀ MatrixOﬀ Schematics LED Enable Matrix LED Enable IOPos RxTxPos DEFAULT at Hard Reset MOV R0,WrFlags Tx (if RxTxPos=1) Rx (if RxTxPos=1) + + SAO IN Rx GND 3 2 1 OUT 0 3 2 1 0 GND +3V RES Tx + RESET 0 1 4 Tx Rx 4 0 In: addr 0x0B 1 Out: addr 0x0A InB: addr 0xFB OutB: addr 0xFA Operation: Every bit in the Register WrFlags has its own function: Bit 3: LedsOﬀ = 0 LedsOﬀ = 1 LEDs on the ALU schematics diagram are enabled. LEDs on the ALU panel schematics diagram are turned oﬀ, except LEDs CLK and CLK, which are always on. Bit 2: MatrixOﬀ = 0 LEDs on the Data memory Display Matrix are enabled. MatrixOﬀ = 1 LEDs on the Data memory Display Matrix are turned oﬀ. Bit 1: IOpos = 0 IOPos = 1 Out register is at address 0x0A, In register is at address 0x0B Out register is at address 0xFA, In register is at address 0xFB Bit 0: RxTxPos = 0 UART ports TXD and RXD are available on the SAO connector, and all Input and Output ports are on the main I/O connector. RxTxPos = 1 UART ports TXD and RXD are on the main connector (pins 2 and 3 from the left), RX pin on the SAO connector is inactive. TX pin on SAO connector still has TX function. Input port (which is always readable on the address 0x0A or 0XFA) is normally active, reading bit0 and bit1, and also current states from bit2 (Rx) and bit3 (Tx). Supplyframe, Inc. 14 Special Function Register SFRF4 (RdFlags) Description: 0xF4 Register RdFlags contains individual status ﬂags. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV RdFlags,R0 READING: INSTRUCTION RdFlags RdFlags,3 Unused RdFlags,2 Unused 0 0 RdFlags,1 RdFlags,0 Vﬂag UserSync R 0 S MOV R0,RdFlags Reset on every reading Set/Reset Vﬂag according to the operation in Adder Uniform Clock R 0 S DEFAULT at every Hard Reset, program RUN and stop Set on Sync counter underﬂow Sync Counter (COUNTDOWN) Reloaded on Sync counter underﬂow SFR 0xF2 (Sync) WRITING: INSTRUCTION MOV Sync,R0 R0 Operation: Register RdFlags signiﬁes statuses for the following events: Bit 3: Unused Bit 2: Unused Bit 1: Vﬂag = 0 Vﬂag = 1 V ﬂag not set (signed arithmetic operation was in range) V ﬂag is set (signed arithmetic operation was out of range and the result of the operation is incorrect) Bit 0: UserSync = 0 User Sync didn’t occur yet. UserSync = 1 User Sync occurred. This bit is automatically reset upon reading of the register RdFlags. Note: Period for UserSync function can be selected by writing the value to the register Sync. Supplyframe, Inc. 15 Special Function Register SFRF5 (SerCtrl) Description: 0xF5 Register SerCtrl contain the ERROR bit for the Serial Port and determines the Baud Rate. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV SerCtrl,R0 READING: INSTRUCTION SerCtrl,3 SerCtrl,2 SerCtrl,1 SerCtrl,0 0 0 1 1 SerCtrl R Error S Baud Rate Index MOV R0,SerCtrl DEFAULT at every Hard Reset, program RUN and stop Reset after every reading Overrun Error Framing Error FIFO error Baud Rate Divider Fosc UART Operation: Bit 3 is used to determine if the error occurred during UART operation. This bit is automatically reset on every reading of register RdFlags. Bits #2, #1 and #0 determine the Baud Rate for the UART. Here is the table of the available Baud rates: Supplyframe, Inc. # BIT BIT BIT #2 #1 #0 Baud 0 0 0 0 1200 1 0 0 1 2400 2 0 1 0 4800 3 0 1 1 9600 4 1 0 0 19200 5 1 0 1 38600 6 1 1 0 57600 7 1 1 1 115200 16 DEFAULT Special Function Register SFRF6 (SerLow) Description: Register SerLow consists of two 4-bit registers which share the same address, but one of them is read-only, and the other one write-only. The ﬁrst one is automatically loaded with the low nibble when the serial data byte is received, and another one is used for writing the low nibble of the data byte which will be immediately and automatically transmitted. There is the similar register pair SFRF7 which is used for the high nibble of data byte. HIGH NIBBLE SerHigh READING: INSTRUCTION 0xF6 RXD RXD LOW NIBBLE SerLow,3 RXD SerLow,2 RXD SerLow,1 RXD SerLow,0 RXD FIFO 256 bytes MOV R0,SerLow Move From FIFO to SerLow Decrement SFR8 (Received) WRITING: INSTRUCTION R0 Increment SFR 0xF8 (Received) MOV SerLow,R0 UART START TRANSMIT TXD These registers are described on the next page SerHigh TXD SerLow,#3 SerLow,#2 SerLow,#1 SerLow,#0 TXD TXD TXD TXD Power On and Run default values for all registers represented here are 0000. Operation: This is not a single register but a pair of registers. They are on the same address, but one of them is read-only, and the other one is write-only. We will call them SerLow-r and SerLow-w here, although they share the same name. Transmitting is a simple operation, as the handshaking protocol between the processor and UART is straightforward. Processor tests if the transmitter is ready (if the last byte was transmitted) and, if so, writes SerLow-w (low nibble) and SerHigh-w (high nibble) to the 8-bit transmit buﬀer. If it’s not ready, it will wait until the transmission is ﬁnished. This can cause certain slowing down in program ﬂow. Note that the automatic transmission occurs only when the low nibble is written to SerLow-w, and not when the high nibble is written to SerHigh-w. For that reason, it is a good practice to write to the high nibble register (SerHigh-w) ﬁrst. When UART receives the data byte, it writes the byte into the 256-byte FIFO (First In - First Out) buﬀer. If the whole FIFO buﬀer is full (256 unread bytes), the following bytes are lost and the Error (SerCtrl,#3) ﬂag is set. In the concurrent process, if the SerLow-r register is empty (data nibble was read), the new byte is written to SerLow-r (low nibble) and SerHigh-r (high nibble). At that moment, the register SFR8 (Received) will be automatically decremented. Note that all that happens automatically. All that the user’s program has to do, is to test if the register Received is greater than 0 and, if it is (which is the sign that the new byte arrived from the serial port), read the high nibble (SerHigh-r) ﬁrst, and then the low nibble (SerLow-r). Reading the low nibble (SerLow-r) resets the ﬂag RxRdy automatically. This is not the case with high nibble reading (SerHigh-r), so it is a good practice to read the high nibble (SerHigh-w) ﬁrst. Supplyframe, Inc. 17 Special Function Register SFRF7 (SerHigh) Description: 0xF7 Register SerHigh consists of two 4-bit registers which share the same address, but one of them is read-only, and the other one write-only. The ﬁrst one is automatically loaded with the high nibble when the serial data byte is received, and another one is used for writing the high nibble of the data byte which will be transmitted. There is the similar register pair SFR6 which is used for the low nibble of data byte. READING: INSTRUCTION MOV R0,SerHigh HIGH NIBBLE LOW NIBBLE SerHigh,3 SerHigh,2 SerHigh,1 SerHigh,0 RXD RXD RXD RXD SerLow RXD RXD FIFO 256 bytes R0 WRITING: INSTRUCTION UART These registers are described on the previous page TXD MOV SerHigh,R0 SerHigh,#3 SerHigh,#2 SerHigh,#1 SerHigh,#0 TXD TXD TXD TXD SerLow TXD Power On and Run default values for all registers represented here are 0000. Operation: This is not a single register but a pair of registers. They are on the same address, but one of them is read-only, and the other one is write-only. We will call them SerHigh-r and or SerHigh-w here, although they share the same name. Transmitting is a simple operation, as the handshaking protocol between the processor and UART is straightforward. Processor tests if the transmitter is ready (if the last byte was transmitted) and, if so, writes SerHigh-w (high nibble) and SerLow-w (low nibble) to the 8-bit transmit buﬀer. If it’s not ready, it will wait until the transmission is ﬁnished. This can cause certain slowing down in program ﬂow. Note that the automatic transmission occurs only when the low nibble is written to SerLow-w, and not when the high nibble is written to SerHigh-w. For that reason, it is a good practice to write to the high nibble register (SerHigh-w) ﬁrst. When UART receives the data byte, it writes the byte into the 256-byte FIFO (First In - First Out) buﬀer. If the whole FIFO buﬀer is full (256 unread bytes), the following bytes are lost and the Error (SerCtrl,#3) ﬂag is set. In the concurrent process, if the SerLow-r register is empty (data nibble was read), the new byte is written to SerLow-r (low nibble) and SerHigh-r (high nibble). At that moment, the register Received will be automatically decremented. Note that all that happens automatically. All that the user’s program has to do, is to test if the register Received is greater than 0 and, if it is (which is the sign that the new byte arrived from the serial port), read the high nibble (SerHigh-r) ﬁrst, and then the low nibble (SerLow-r). Reading the low nibble (SerLow-r) resets the ﬂag RxRdy automatically. This is not the case with high nibble reading (SerHigh-r), so it is a good practice to read the high nibble (SerHigh-w) ﬁrst. Supplyframe, Inc. 18 Special Function Register SFRF8 (Received) Description: Register Received contains 4-bit count of bytes in the FIFO queue plus one byte in SerLow-SerHigh pair (only SerLow contains the internal handshaking logic, and SerHigh is assumed). The capacity of FIFO and SerLow - SerHigh pair is 257 bytes total, so register Received shows the real number for 0-14 bytes, and state “15” means “15 or more”. bit WRITING: INSTRUCTION 0xF8 3 2 1 0 R0 MOV Received,R0 READING: INSTRUCTION Received Received,3 Received,2 0 0 MOV R0,Received Received,1 Received,0 1 1 DEFAULT at every Hard Reset, program RUN and stop Operation: register Received is incremented every time when the byte is received and transferred from th UART to the FIFO memory, which is in the Data Memory of the microcontroller, and driven by the ﬁrmware. When the nibble is read from the register SerLow, register Received is decremented. So it shows the number of received, but unread bytes. Handshaking between SerLow-SerHigh pair and FIFO buﬀer is performed internally, and the ﬁrmware takes care about it. All that user’s program has to do is to read the state of register Received and test its zero-state: if it is greater than 0, reading is allowed and user is sure that it will not be read more than once. The capacity of FIFO and SerLow-SerHigh pair is 257 bytes total, and the register Received shows the real number for 0-14 bytes, and state “15” means “15 or more”. Note: After reading from SerLow, register Received will be decremented automatically. User’s program should never attempt to modify it. Supplyframe, Inc. 19 Special Function Register SFRF9 (AutoOﬀ) Description: 0xF9 Register AutoOﬀ is the 4-bit down-counter which is decremented automatically at every 10 minutes. When it reaches zero, the device is internally rendered to SLEEP mode. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV AutoOﬀ,R0 AutoOﬀ READING: INSTRUCTION AutoOﬀ,3 AutoOﬀ,2 AutoOﬀ,1 AutoOﬀ,0 0 1 0 1 1 1 0 1 MOV R0,AutoOﬀ at wake-up and reset at every keystroke Operation: Register AutoOﬀ is the 4-bit counter which is decremented by 1 on every 10 minutes. It is driven by the internal prescaler which divides the system oscillator frequency and thus generates one pulse at every 10 minutes. Every time when the register AutoOﬀ is loaded with the new value, the prescaler is preset to the full 10 minutes period. The only exception is when the user’s program writes 0 to the register AutoOﬀ, then the prescaler is is not pre-loaded, which means that the unit will be shut oﬀ (rendered to SLEEP mode) immediately. When the register AutoOﬀ reaches zero, the device is internally rendered to SLEEP mode. It is the equivalent of switching the unit oﬀ by pressing OFF-ON button. Register AutoOﬀ allows that the user’s program can keep the unit always ON (writing some high value, e.g. 1111 often enough) or to switch it oﬀ immediately, writing the zero value. Supplyframe, Inc. 20 Special Function Register SFRFA (OutB) Description: 0xFA Register OutB is the alternate 4-bit latch for output port, active when the WrFlag,1 bit (IOPos) is set. bit WRITING: INSTRUCTION 3 2 1 0 OutB,3 OutB,2 OutB,1 OutB,0 0 0 0 0 R0 MOV OutB,R0 OutB READING: INSTRUCTION at hard reset MOV R0,OutB I/O CONNECTOR PINS OUTPUT Operation: This register is the output latch. Contents written in the register OutB will appear on the connector output pins as logic levels. Note: This register is active only when the WrFlag,1 bit (IOPos) is set. Otherwise, this register may be used as the normal memory location, and the register Out (address 0x0A) is active. Supplyframe, Inc. 21 Special Function Register SFRFB (InB) Description: 0xFB Register InB is the alternate In register, active when the WrFlag,1 bit (IOPos) is set. bit WRITING: INSTRUCTION 3 2 1 0 InB,3 InB,2 InB,1 InB,0 0 0 0 0 R0 MOV InB,R0 InB READING: INSTRUCTION at hard reset MOV R0,InB IOPos SWITCHOVER (reg WrFlags, bit 1) + I/O CONNECTOR PINS INPUT Operation: This register is the input port register. Logical levels on the connector input pins are always transferred to the register InB. Note: This register is active only when the WrFlag,1 (bit IOPos) is set. Otherwise, this register may be used as the normal memory location. If the WrFlag,1 (bit IOPos) is set, the register In (address 0x0B) is active. Note: When the register InB is selected as the input port (when the WrFlag,1 (bit IOPos) is set), writing to this register is possible, but the contents will be instantly overwritten. So it makes no sense, except for dummy writes. Supplyframe, Inc. 22 Special Function Register SFRFC (KeyStatus) Description: 0xFC Register RS3 contains individual statuses for registers RS0, RS1 and RS2 in bits RS3,#2, RS3,#1 and RS3,#0. If the contents of these registers is 0000, the corresponding bit will be 0. Otherwise, the corresponding bit will be 1. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV KeyStatus,R0 Alt key KeyStatus READING: INSTRUCTION Key # denoted in register KeyReg Any key KeyStatus, KeyStatus, KeyStatus, KeyStatus, 3 2 1 0 0 AltPress 0 1 1 AnyPress LastPress JustPress R S DEFAULT at every Hard Reset, program RUN and stop MOV R0,KeyStatus Bit 0 is automatically cleared after every reading SFR 0xFD KeyReg Any key Operation: Register KeyStatus allows the program to read the status of certain buttons of the keyboard. Bit 3: AltPress = 0 AltPress = 1 Button ALT not pressed (debounced, 5 ms delay) Button ALT pressed (debounced, 5 ms delay) Bit 2: AnyPress = 0 No button is pressed (buttons ALT and ON-OFF not tested) AnyPress = 1 At least one button is pressed (buttons ALT and ON-OFF not tested) Bit 1: LastPress = 0 The last pressed button (written in register KeyReg) is not pressed LastPress = 1 The last pressed button (written in register KeyReg) is pressed Bit 0: JustPress = 0 No button was pressed after last reading of this register. JustPress = 1 Button (which is written in register KeyReg) was pressed, and this bit is automatically reset after reading this register. So this bit can be read only once after every keypress. Bits 3, 2 and 1 show the momentarily state of buttons and every of them is automatically reset to 0 as soon as the condition for 1 is not satisﬁed any more Bit 0 is the handshaking bit: once it is set, it will not be reset until this register is read. Then it is automatically reset, which means that the state “1” of this bit can be read only once after every keypress. Supplyframe, Inc. 23 Special Function Register SFRFD (KeyReg) Description: 0xFD Register KeyReg contains the number of the last pressed button. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV KeyReg,R0 KeyReg,3 KeyReg,2 KeyReg 0 READING: INSTRUCTION KeyReg,1 KeyReg,0 0 0 at hard reset 0 MOV R0,KeyReg Operation: This register contains the number of the last pressed button. The contents will not change when the button is released, but only when the next button is pressed. Here is the list of buttons, with the corresponding numbers. Pressing On-Oﬀ, ALT or any button in the Mode Speciﬁc Command group do not aﬀect this register. These buttons are marked as “NOT USED” here. ALT MODE CARRY HISTORY FAST 0 LOAD - ADDR + BREAK - ADDR + OPCODE CLOCK OPERAND X OPERAND Y DATA IN STEP RUN DEP+ 8 4 2 1 8 4 2 1 8 4 NOT NOT NOT NOT USED USED USED USED 1 2 3 4 5 6 7 8 9 10 11 12 ADDR SET NOT USED SAVE PAUSE DIM CLOCK NOT ON USED OFF Supplyframe, Inc. 24 2 PAGE 1 13 Special Function Register SFRFE (Dimmer) Description: 0xFE Register Dimmer contains 4-bit value for the PWM LED intensity control. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV Dim,R0 READING: INSTRUCTION Dimmer Dimmer,3 Dimmer,2 1 Dimmer,1 Dimmer,0 1 1 1 DEFAULT at Hard Reset MOV R0,Dim PWM Operation: All LEDs are arranged in 16×17 matrix, which is under the software control of the system microcontroller PIC24FJ256GA704-I/PT. Register Dimmer controls the Pulse Width Modulation ratio for ON/OFF state of all LEDs. Value 1111 results in the 100% duty cycle, which is the brightest setting. Value "0000" results in the lowest light level. Supplyframe, Inc. 25 Special Function Register SFRFF (Rnd) Description: 0xFF Register Rnd contains the dynamic 4-bit pseudorandom value. bit WRITING: INSTRUCTION 3 2 1 0 R0 MOV Rnd,R0 A 1111 B Comparator A=B + Pseudorandom Number Generator Hardware Scrambler (TMR1, TMR2, Int count, Uninitialized Data memory) READING: INSTRUCTION Rnd Rnd,3 Rnd,2 Rnd,1 Rnd,0 MOV R0,Rnd Operation: 4-bit pseudorandom value is generated by the 32-bit Linear Congruential Generator, which uses the formula: Xn+1=(a×Xn + c) mod 232 ( a = 0x41C64E6D, c = 0x6073 ) Seed X0 is generated at Master Reset, using the uninitialized Data Memory data at startup. The same seed can be reinitialized to the known value by writing to the register Rnd. This value contains only 4 bits, but it is written in all 8 nibbles of Rnd, so all the subsequent values are predictable. For instance, if the value written to Rnd is 0001 binary, the value of 32-bit Seed will be 00010001 00010001 00010001 00010001. There is an exception, when the binary value written to the register Rnd is 1111 (decimal 15), the full scrambled value will be rewritten to all 32 bits of Seed, and all the subsequent numbers will be unpredictable. This is the default behaviour of the Rnd register. After every read from the SFR register Rnd, the new pseudorandom cycle Xn+1=(Xn×0x41C64E6D + 0x6073) mod 232 is executed and bits 3-0 of Seed are rewritten to the register Rnd. There is one more a way to initiate the Pseudorandom cycle and write the new unpredictable value to the register Rnd. When the unit is in SS mode, and the register Page is 1111 (decimal 15), every press of the button Data In will cause the new value in the register Rnd. Note: Default value for Rnd register is randomly preset at power-up. Supplyframe, Inc. 26