Manual / Guide · 2022

Supplyframe 4-Bit Processor Badge — Instruction Set

Author: Supplyframe, Inc.
Year: 2022
Type: Manual / Guide

instruction set
opcodes
assembly
4-bit processor
supplyframe

INSTRUCTION SET Revision 4 Nov-02-2022 Supplyframe, Inc. CODING CODE OPC MNEMONIC FLAGS 1 ADD RX,RY V Z C 2 ADC RX,RY V Z C 3 SUB RX,RY V Z C 4 SBB RX,RY V Z C 5 OR RX,RY Z 6 AND RX,RY Z 7 XOR RX,RY Z 8 MOV RX,RY 9 MOV RX,#N A MOV [XY],R0 B MOV R0,[XY] C MOV [NN],R0 D MOV R0,[NN] E MOV PC,NN F JR NN 00 CP R0,N V Z C 01 ADD R0,N V Z C 02 INC RY Z C 03 DEC RY Z C 04 DSZ RY 05 OR R0,N Z C 06 AND R0,N Z C 07 XOR R0,N Z C 08 EXR N 09 BIT RG,M 0A BSET RG,M 0B BCLR RG,M 0C BTG RG,M 0D RRC RY 0E RET R0,N 0F SKIP F,M Z C Z C OPERAND X OPCODE OPCODE 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X N N N N 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X N N N N 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X N N N N 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X X X X X X X X X X N N N N 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OPERAND Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N N N Y Y Y Y Y Y Y Y N N N N N N N N N N N N N N N N N N N N N N N N Y Y Y Y Y Y Y Y Y Y Y Y N N N N N N N N N N N N N N N N G G M M G G M M G G M M G G M M Y Y Y Y N N N N F F M M Note: Modes SS and RUN support all instructions, and ALU mode supports only instructions with triangular sign " ", but not in the same way as SS and RUN modes. Please refer to the section “INSTRUCTIONS IN ALU MODE”. Supplyframe, Inc. 2 ADD RX,RY Add registers RX and RY Syntax: {label} ADD Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) + (RY) Description: Add the contents of the register RY to the contents of the register RX and place the result in the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: If there is the overﬂow (if (RX)+(RY)>15), set C. Otherwise, reset C. If result=0000 after operation, set Z. Otherwise, reset Z. For signed 2’s complement arithmetic: If there is overﬂow, set V. Otherwise, reset V. Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 X X X X Y Y Y Y The "0001" bits are the ADD RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: ADD R2, R0 Flag Z 1 0 Flag V 0 Flag C R0 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 0 0 0 0 OPCODE 0001 = ADD OPERAND RY 1 0 0 1011 UNSIGNED (decimal) R1 R2 OPERAND RX SIGNED (decimal) 1011 11 - 5 R4 R5 V Flag 1 0 1 1 R0 R1 R3 R4 0111 + 7 +7 R6 R7 Z Flag 0 0 1 0 R2 0111 R3 C Flag R5 R6 0010 =2 2 R7 R8 R8 R9 R9 OUT OUT IN JSR PCL PCM PCH Before operation Supplyframe, Inc. IN Note: Carry ﬂag is set (C=1), which means that the result is not correct for unsigned operation. But the V ﬂag is reset, so the result (2) is correct for signed operation. Note: If both operands are the same, instruction ADD RX,RY can be used as a substitute for the instruction SL RY (Shift RY Left) 3 JSR PCL PCM PCH After operation ADC RX,RY Add with carry registers RX and RY Syntax: {label} ADC Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) + (RY) + Carry Description: Add the contents of the register RY plus the contents of Carry ﬂag to the contents of the register RX and place the result in the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: If there is the underﬂow (if (RY)<(RX)), reset C. Otherwise, set C. (note: Borrow is inverse C). If result=0000 after operation, set Z. Otherwise, reset Z. For signed 2’s complement: If there is overﬂow, set V. Otherwise, reset V. Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 X X X X Y Y Y Y The "0010" bits are the ADC RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: ADC R1, R7 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 1 0 1 1 1 OPCODE 0010 = ADC Flag Z 1 0 Flag V 0 Flag C OPERAND RY 1 1 0 R0 R1 OPERAND RX UNSIGNED (decimal) 0100 SIGNED (decimal) R2 Z Flag V Flag R0 0 0 0 0 R1 R2 0100 R3 4 4 R4 R3 R4 R5 1011 + 11 + (- 5) 1 + 1 + 1 R6 R7 C Flag R5 R6 1011 R8 R9 1 1 1 0 R7 R8 0000 =0 - 0 R9 OUT OUT IN IN JSR JSR PCL PCL PCM PCH Hint: If both operands are the same, instruction ADC RX,RY can be used as a substitute for the instruction RLC RY (Rotate Left RY Through Carry) Before operation Supplyframe, Inc. PCM PCH After operation 4 SUB RX,RY Subtract register RY from register RX Syntax: {label} SUB Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) - (RY) Description: Subtract the contents of the register RY from the contents of the register RX and place the result in the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: If there is the underﬂow (if (RY)<(RX)), reset C. Otherwise, set C. (note: Borrow is inverse C). If result=0000 after operation, set Z. Otherwise, reset Z. For signed 2’s complement: If there is overﬂow, set V. Otherwise, reset V. Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 X X X X Y Y Y Y The "0011" bits are the SUB RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example 1: SUB R6, R2 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 0 1 1 0 0 0 1 0 OPCODE 0011 = SUB Flag Z 0 0 Flag V 0 Flag C OPERAND RX OPERAND RY 1 0 0 R0 1001 R3 1111 UNSIGNED (decimal) SIGNED (decimal) 15 -1 R4 V Flag R1 1 0 0 1 R2 R3 R4 R5 R6 Z Flag R0 R1 R2 C Flag 1001 -9 - (- 7) 0 1 1 0 R6 1111 R7 R8 R5 R7 0110 = 6 6 R8 R9 R9 OUT OUT IN IN JSR JSR Note: For subtraction, Carry ﬂag is called Borrow, and it PCL is actually inverse Carry. So, No-Carry (if C=0) means PCM "Borrow", and Carry (C=1) means "No Borrow". In this example the resulting C=1, so the result is correct in PCH unsigned representation. Flag V is reset, which means Before operation that the result is correct in signed representation also. Supplyframe, Inc. 5 PCL PCM PCH After operation SUB RX,RY Subtract register RY from register RX (CONTINUED) Example 2: SUB R10, R4 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 0 1 0 0 1 0 0 OPCODE 0011 = SUB Flag Z 1 0 Flag V 0 Flag C OPERAND RX OPERAND RY 0 0 0 C Flag Z Flag V Flag R0 R0 R1 R1 R2 R2 UNSIGNED (decimal) R3 R4 SIGNED (decimal) 0111 0 1 1 1 R4 0101 R5 5 5 R6 R5 R6 0111 R7 -7 - (+ 7) R8 R7 R8 R9 OUT R3 0101 1110 = 14 - 2 R9 1 1 1 0 OUT IN IN JSR JSR PCL PCL PCM PCM PCH PCH Before operation After operation Note: For subtraction, Carry ﬂag is called Borrow, and it is actually inverse Carry. So, No-Carry (if C=0) means "Borrow", and Carry (C=1) means "No Borrow". In this example C=0, so there is Underﬂow condition, which means that the result is not correct in unsigned representation. In signed representation, the result is 1110, which is -2. Flag V is not set, which means that -2 is the correct result. Supplyframe, Inc. 6 SBB RX,RY Subtract register RY from register RX with borrow Syntax: {label} SBB Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) - (RY) - (C) Description: Subtract the contents of the register Y from the contents of the register X and place the result in the register X. Register direct addressing must be used for X and Y. Flags aﬀected: If there is the underﬂow (if (RY)<(RX)), reset C. Otherwise, set C. (note: Borrow is inverse C). If result=0000 after operation, set Z. Otherwise, reset Z. For signed 2’s complement: If there is overﬂow, set V. Otherwise, reset V. Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 X X X X Y Y Y Y The "0100" bits are the SBB RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example 1: SBB R5, R3 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 1 0 0 1 1 OPCODE 0100 = SBB Flag Z 0 0 Flag V 0 Flag C OPERAND RX OPERAND RY 1 0 0 R0 UNSIGNED (decimal) SIGNED (decimal) R2 V Flag R1 R2 0011 1110 14 - 2 R4 R5 Z Flag R0 R1 R3 C Flag 0 0 1 1 R3 R4 1110 0011 - 3 - (+3) R6 R7 R6 1 - 1 - 1 R8 R7 R8 R9 OUT 1 0 1 0 R5 R9 1010 = 10 - 6 OUT IN IN JSR JSR PCL PCL PCM PCH Before operation Supplyframe, Inc. Note: For subtraction, Carry ﬂag is called Borrow, and it is inverse Carry. In this example the resulting ﬂags are C=1 and V=0, which means that the result is correct both for unsigned and in signed representations. 7 PCM PCH After operation SBB RX,RY Subtract register RY from register RX with borrow (CONTINUED) Example 2: SBB R6, R7 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 1 1 0 0 1 1 1 OPCODE 0100 = SBB Flag Z 1 0 Flag V 0 Flag C OPERAND RX OPERAND RY 0 0 1 C Flag Z Flag V Flag R0 R0 R1 R1 R2 UNSIGNED (decimal) R3 SIGNED (decimal) R4 R2 R3 R4 0110 R5 R6 0110 R7 1110 6 6 1 0 0 0 R6 1110 - 14 - (- 2) R8 R9 1 1 1 0 R7 R8 0 - 0 - 0 OUT IN R5 R9 OUT 1000 =8 - 8 IN JSR JSR PCL PCL PCM PCM PCH PCH Before operation After operation Note: For subtraction, Carry ﬂag is called Borrow, and it is actually inverse Carry. So, No-Carry (C=0) means "Borrow", and Carry (C=1) means "No Borrow". In this example the resulting ﬂag C=0, so there is Underﬂow condition, which means that the result is not correct in unsigned representation. The Overﬂow ﬂag is set (V=1), which means that the result is not correct even in signed representation. Supplyframe, Inc. 8 OR RX,RY Inclusive OR registers RX and RY Syntax: {label} OR Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) .OR. (RY) Description: Compute the logical inclusive OR operation of the 4-bit register RX with register RY and place the result back into the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: Flag C is not aﬀected If result=0000 after operation, set Z. Otherwise, reset Z Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 X X X X Y Y Y Y The "0101" bits are the OR RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: OR R0, R7 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 0 0 1 1 1 OPCODE 0101 = OR Flag C Flag Z Flag V R0 OPERAND RX OPERAND RY 0 0 0 0 1 0 C Flag Z Flag V Flag 1 1 0 1 R0 0101 R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 R6 R7 1101 R8 0101 5 1100 .OR. 12 R9 OUT R6 1 1 0 1 R7 R8 R9 1101 = 13 OUT IN IN JSR JSR PCL PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 9 AND RX,RY Logical AND registers RX and RY Syntax: {label} AND Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) .AND. (RY) Description: Compute the logical AND operation of the 4-bit register RX with register RY and place result back into the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: Flag C is not aﬀected If result=0000 after operation, set Z. Otherwise, reset Z Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 X X X X Y Y Y Y The "0110" bits are the AND RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 1 0 1 0 1 0 1 1 AND R10, R11 OPCODE 0110 = AND Flag C Flag Z Flag V OPERAND RX 0 1 0 OPERAND RY 0 0 0 C Flag Z Flag V Flag R0 R0 R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 R6 R6 R7 R7 R8 R8 1110 R9 OUT 1110 IN 0111 14 0 1 1 1 .AND. 7 JSR PCL R9 0 1 1 0 OUT 0 1 1 1 IN JSR 0110 = 6 PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 10 XOR RX,RY Exclusive OR registers RX and RY Syntax: {label} XOR Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RX) .XOR. (RY) Description: Compute the logical exclusive XOR operation of the 4-bit register RX with register RY and place the result back into the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: Flag C is not aﬀected If result=0000 after operation, set Z. Otherwise, reset Z Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 X X X X Y Y Y Y The "0111" bits are the XOR RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: XOR R8, R3 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 0 0 0 0 0 1 1 OPCODE 0111 = XOR OPERAND X OPERAND Y 0 0 C Flag Flag Z 0 1 Flag V 0 0 V Flag Flag C Z Flag R0 R0 R1 R1 R2 R2 R3 1 1 0 0 R3 1100 R4 R4 R5 R5 0110 R6 6 R7 R8 R6 R7 0110 1 1 0 0 .XOR.12 R9 OUT 1 0 1 0 R8 R9 1010 = 10 OUT IN IN JSR JSR PCL PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 11 MOV RX,RY Move contents from register RY to register RX Syntax: {label} MOV Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (RX) ← (RY) Description: Move the 4-bit contents from the register RY to the register RX. Register direct addressing must be used for RX and RY. Flags aﬀected: None. Encoding: RX, RY bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 X X X X Y Y Y Y The "1000" bits are the MOV RX,RY opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: MOV R6, R5 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 1 1 0 0 1 0 1 OPCODE 1000 = MOV Flag C Flag Z Flag V OPERAND RX OPERAND RY 0 0 0 0 0 0 C Flag Z Flag V Flag R0 R0 R1 R1 R2 R2 R3 R3 R4 R4 0 0 1 0 R5 0 0 1 0 R6 0010 R6 1 1 1 0 R5 R7 R8 R9 Note: Contents of the source operand has NOT changed. This rule is valid for all instructions; only the destination register is modiﬁed by the operation. R7 R8 R9 OUT OUT IN IN JSR PCL PCM PCH Note: If the instruction MOV RX,RY has the register JSR (0x0C) or PCL (0x0D) as the destination, then Subroutine Call or Program Jump will be executed. Please read the main User’s Manual. Before operation Supplyframe, Inc. JSR PCL PCM PCH After operation 12 MOV RX,N Move 4-bit literal N to register RX Syntax: {label} MOV Operands: RX ∈ [R0...R15] N ∈ 0...15 Operation: (RX) ← N Description: Move the 4-bit literal to the register RX. Register direct addressing must be used for RX Flags aﬀected: None. Encoding: RX, N bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 X X X X N N N N The "1001" bits are the MOV RX,N opcode The "XXXX" bits select the operand RX The "NNNN" bits are the literal N Example: MOV R9, 7 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 0 0 1 0 1 1 1 OPCODE 1001 = MOV RX,N Flag C Flag Z Flag V OPERAND RX LITERAL N 0 0 0 0 0 0 C Flag Z Flag V Flag R0 R0 R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 R6 R6 R7 R7 R8 R8 R9 0 1 1 1 R9 1010 OUT OUT IN IN JSR PCL PCM Note: If the instruction MOV RX,N has the register JSR (0x0C) or PCL (0x0D) as the destination, then Subroutine Call or Program Jump will be executed. Please read the main User’s Manual. PCH PCL PCM PCH Before operation Supplyframe, Inc. JSR After operation 13 Move contents of register R0 to data memory indirectly MOV [XY],R0 addressed by register RX (high nibble) and RY (low nibble) Syntax: {label} MOV Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: ((RX):(RY)) ← (R0) Description: Move the 4-bit contents of register R0 to data memory indirectly addressed by registers RX (high nibble) and RY (low nibble). Register direct addressing must be used for RX and RY. Flags aﬀected: None. Encoding: [XY], R0 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 X X X X Y Y Y Y The "1010" bits are the MOV [XY],R0 opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: MOV [R6:R4],R0 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 0 0 1 0 1 0 0 OPCODE 1010 = MOV [XY],R0 OPERAND RY 0 0 0 Flag C Flag Z Flag V 0 0 0 R0 DATA MEMORY 0101 OPERAND RX 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 ... Before operation Supplyframe, Inc. C Flag Z Flag V Flag 1111 DATA MEMORY R1 R2 R3 R4 0010 3 R5 0010 R6 Bit R7 3 0 0001 R8 R9 0 0001 Bit 7 0 OUT 0001 0010 IN DATA MEMORY ADDRESS JSR PCL 1111 PCM PCH Unchanged 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 ... After operation 14 Move contents of data memory indirectly addressed by MOV R0,[XY] register RX (high nibble) and RY (low nibble) to register R0 Syntax: {label} MOV R0, [XY] Operands: RX ∈ [R0...R15] RY ∈ [R0...R15] Operation: (R0) ← ((RX):(RY)) Description: Move the 4-bit contents of data memory indirectly addressed by register RX (high nibble) and RY (low nibble) to register R0. Register direct addressing must be used for RX and RY. Flags aﬀected: None. bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 X X X X Y Y Y Y Encoding: The "1011" bits are the MOV R0,[XY] opcode The "XXXX" bits select the operand RX The "YYYY" bits select the operand RY Example: bit 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 1 0 0 0 1 1 1 MOV R0, [R4:R7] OPCODE 1011 = MOV R0,[XY] Flag C Flag Z Flag V R0 OPERAND RX 0 0 0 0 0 0 DATA MEMORY R2 0x00 0x01 0x02 0x03 0x04 0x05 ... R3 0101 R5 Bit 3 0 0101 R6 R7 3 1010 0 1010 R8 R9 Bit 7 0 OUT 0101 1010 IN DATA MEMORY ADDRESS JSR 1110 PCL PCM PCH Before operation Supplyframe, Inc. C Flag Z Flag V Flag 1 1 1 0 R0 0011 R1 R4 OPERAND RY ... 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D ... Unchanged 15 R1 R2 R3 0 1 0 1 R4 R5 R6 1 0 1 0 R7 R8 R9 OUT IN JSR PCL PCM PCH After operation Move contents of register R0 to data memory MOV [NN],R0 addressed by literal NN Syntax: {label} MOV Operands: NN ∈ [0...255] Operation: (NN) ← (R0) Description: Move the 4-bit contents of register R0 to data memory addressed by unsigned literal [NN]. Flags aﬀected: None. Encoding: [NN], R0 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 N N N N N N N N The "1100" bits are the MOV [NN],R0 opcode The "NNNNNNNN" bits are unsigned literal NN Example: MOV [0x19], R0 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 0 C Flag OPCODE 1100 = MOV [NN],R0 0 0 0 Flag Z Flag V DATA MEMORY 1 0 0 1 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A ... R0 V Flag DATA MEMORY 1001 R1 R2 R3 R4 R5 R6 R7 R8 R9 OUT IN JSR PCL PCM PCH Unchanged 1001 Note: R0 is the only register that can be used in this instruction. Before operation Supplyframe, Inc. Z Flag DATA MEMORY ADDRESS Flag C 0111 LITERAL NN 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A ... After operation 16 Move contents of data memory addressed by literal NN to register R0 MOV R0,[NN] Syntax: {label} MOV Operands: NN ∈ [0...255] Operation: (R0) ← (NN) Description: Move the 4-bit contents of data memory addressed by unsigned literal NN to register R0. Register direct addressing must be used for R0. Flags aﬀected: None. Encoding: R0, [NN] bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 N N N N N N N N The "1101" bits are the MOV R0,[NN] opcode The "NNNNNNNN" bits are unsigned literal NN Example: MOV R0, [0xE2] bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 1 1 1 0 0 0 1 0 0 0 0 C Flag OPCODE 1101 = MOV R0,[NN] Flag C Flag Z Flag V R0 LITERAL NN 0 0 0 DATA MEMORY R1 R2 0x00 0x01 0x02 0x03 0x04 0x05 ... R6 R7 R8 R9 OUT DATA MEMORY ADDRESS R3 R5 IN JSR 1110 PCL PCM PCH Before operation ... 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 ... Unchanged Note: R0 is the only register that can be used in this instruction. Supplyframe, Inc. V Flag 1 1 1 0 R0 0011 R4 Z Flag 17 R1 R2 R3 R4 R5 R6 R7 R8 R9 OUT IN JSR PCL PCM PCH After operation MOV PC,NN Load 8-bit literal to registers PCM and PCH Syntax: {label} MOV PC, NN Operands: NN ∈ [0...255] PCM = [R14] PCH = [R15] Operation: (R14) ← NN bit3...bit0, (R15) ← NN bit7...bit4 Description: Move bits 3..0 of the 8-bit literal NN to R14, and bits 7...4 to R15. Flags aﬀected: None. Encoding: bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 N N N N N N N N The "1110" bits are the LPC #NN opcode The "NNNNNNNN" bits are literal #NN Example: MOV PC,0x31 bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 1 1 0 0 0 1 OPCODE 1110 = LPC Flag C Flag Z Flag V LITERAL NN HIGH LITERAL NN LOW 0 0 0 0 0 0 C Flag Z Flag V Flag R0 R1 R1 R2 R2 ALWAYS POINTS TO PCM, PCH R0 R3 R4 R5 R6 R7 R8 R9 OUT R3 R4 R5 R6 R7 R8 R9 OUT IN IN JSR JSR PCL PCL 0110 PCH 1 0 1 0 0 0 0 1 PCM 0 0 1 1 PCH PCM Before operation Supplyframe, Inc. After operation 18 JR NN Jump relative Syntax: {label} JR Operands: NN ∈ [-128...+127] Operation: Program Counter ← Program Counter + NN signed Description: Add signed integer value NN to the Program Counter Flags aﬀected: None. NN bit 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 N N N N N N N N Encoding: The "1010" bits are the JR NN opcode The "NNNNNNNN" bits are signed literal NN Example: bit 11 10 9 8 7 6 5 4 3 2 1 0 JR -3 1 1 1 1 1 1 1 1 1 1 0 1 OPCODE 1010 = JR LITERAL NN PROGRAM MEMORY ADDRESS WHERE THE INSTRUCTION JR IS bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 Regularly Incremented After Instruction Fetch NEXT PROGRAM MEMORY ADDRESS AFTER FETCHING INSTRUCTION JR bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 1 7 6 5 4 3 2 1 0 1 1 1 1 1 1 0 1 bit Sign Bit 64 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 1 1 1 0 65 -3 = 62 NEW PROGRAM MEMORY ADDRESS Note 1: In this example, where NN = minus 3, program will loop not three, but two instructions back. This is because the Program Counter was already incremented after the JR instruction fetch, before the address calculation took place. Look at the program ﬂow example at the right, program will loop 9× (plus one regular pass) before it skips instruction JR and continues further operation. Note 2: Page crossing is allowed, even if it crosses boundary between address 1111 1111 1111 and 0000 0000 0000, so the address space can be treated as an inﬁnite ring. Supplyframe, Inc. 19 mov dec skip jr R3,10 R3 z -3 CP R0,N Compare register R0 with 4-bit literal Syntax: {label} CP Operands: R0 N ∈ 0...15 Operation: (R0) - N, set ﬂags only Description: Compute unsigned R0 – N and update the C and Z ﬂags. The result of the subtraction is not stored. Flags aﬀected: If (R0) > N or (R0) = N, set C. Otherwise, reset C. If (R0) = N, set Z. Otherwise, reset Z. Encoding: R0, N bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 N N N N The "0000 0000" bits are the CP R0,N opcode The "NNNN" bits are literal N Example: CP R0, 5 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 1 0 1 OPCODE 0000 0000 = CP R0,N LITERAL N 1 1 C Flag Flag Z 0 0 Flag V 0 0 V Flag Flag C R0 0101 0101 5 R1 R2 0 1 0 1 R0 R1 0101 - 5 R3 R2 R3 R4 R5 Z Flag R4 0000 = 0 R5 R6 R6 R7 R7 R8 R8 R9 R9 OUT IN JSR PCL PCM PCH Note: Instruction CP performs unsigned subtraction, but the result is NOT stored, so operand R0 is unchanged after operation. Only ﬂags C and Z are aﬀected. If ﬂag Z is set after operation, it means that R0 = N, and if ﬂag C is set after operation, it means that R0 >= N. Before operation Supplyframe, Inc. OUT IN JSR PCL PCM PCH After operation 20 ADD R0,N Add 4-bit literal to register R0 Syntax: {label} ADD Operands: R0 N ∈ 0...15 Operation: (R0) ← (R0) + N Description: Add the contents of the literal N to the contents of the register R0 and place the result back in the register R0. Flags aﬀected: If there is the overﬂow (if (R0)+N>15), set C. Otherwise, reset C. If result=0000 after operation, set Z. Otherwise, reset Z. Encoding: R0, N bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 N N N N The "0000 0001" bits are the ADD R0,N opcode The "NNNN" bits are literal N Example: ADD R0, 14 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 1 1 1 0 OPCODE 0000 0001 = ADD R0,N LITERAL N 1 1 C Flag Flag Z 0 0 Flag V 0 0 V Flag Flag C R0 0010 0010 2 R1 R2 0 0 0 0 R0 R1 1110 + 14 R3 R2 R3 R4 R5 Z Flag R4 0000 R6 = 16 0000 with C set R5 R6 R7 R7 R8 R8 R9 R9 OUT OUT IN IN JSR JSR PCL PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 21 INC RY Increment register RY by 1 Syntax: {label} INC RY Operand: RY ∈ [R0...R15] Operation: (RY) ← (RY)+1 Description: Add 1 to the contents of the 4-bit register RY and place the result back into the register RY. Flags aﬀected: If result=0000 after operation, set ﬂags Z and C. Otherwise, reset ﬂags Z and C. Encoding: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 Y Y Y Y The "0000 0010" bits are the INC RY opcode The "YYYY" bits select the operand RY Example: INC R3 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 1 1 OPCODE 0000 0010 = INC RY OPERAND RY 1 1 C Flag Flag Z 0 0 Flag V 0 0 V Flag Flag C R0 R0 R1 1111 15 R2 R3 Z Flag R1 R2 1111 1 +1 0 0 0 0 R3 R4 R4 R5 R5 R6 0000 =0 R6 R7 R7 R8 R8 R9 R9 OUT OUT IN JSR PCL Note: If the instruction INC RY modiﬁes the register JSR (0x0C) or PCL (0x0D), then Subroutine Call or Program Jump will be executed. Please read the main User’s Manual. IN JSR PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 22 DEC RY Decrement register RY by 1 Syntax: {label} DEC RY Operand: RY ∈ [R0...R15] Operation: (RY) ← (RY)-1 Description: Subtract 1 from the contents of the 4-bit register RY and place the result back into the register RY. Flags aﬀected: If result=0000 after operation, set ﬂag Z. Otherwise, reset ﬂag Z. If result=1111 after operation, reset ﬂag C. Otherwise, set ﬂag C. Encoding: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 Y Y Y Y The "0000 0011" bits are the DEC RY opcode The "YYYY" bits select the operand RY Example: DEC R8 Flag C Flag Z Flag V bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 1 0 0 0 OPCODE 0000 0011 = DEC RY 0 0 0 OPERAND RY 0 0 0 C Flag Z Flag V Flag R0 R0 R1 R1 R2 0010 2 R3 R2 R3 R4 1 -1 R4 R5 R5 R6 R6 0001 R7 R8 =1 R7 0 0 0 1 R8 0010 R9 R9 OUT OUT IN IN JSR PCL PCM Note: If the instruction DEC RY modiﬁes the register JSR (0x0C) or PCL (0x0D), then Subroutine Call or Program Jump will be executed. Please read the main User’s Manual. PCH PCL PCM PCH Before operation Supplyframe, Inc. JSR After operation 23 DSZ RY Decrement register RY and, if the result is =0, skip the next instruction Syntax: {label} DSZ RY Operands: RY ∈ [R0...R15] Operation: (RY) ← (RY)-1, if result is =0, then PC ← PC+1 Description: Subtract 1 from the contents of the 4-bit register RY and if result is =0, increment Program Counter by 1. Flags aﬀected: None. Encoding: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 Y Y Y Y The "0000 0100" bits are the DSZ RY opcode The "YYYY" bits are operand Y Example: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 1 1 DSZ R3 Flag C Flag Z Flag V OPCODE 0000 0100 = DSZ RY 0 0 0 0001 1 1 -1 R0 OPERAND RY 0 0 0 C Flag Z Flag V Flag R0 R1 R1 R2 R3 0000 R2 =0 0 0 0 0 R3 0001 IF Note: Although it employs subtraction, this instruction does not aﬀect ﬂags. =0 ... HEN S ... T KIP ONE INS TR U ION CT PROGRAM ADDRESS RE SU LT PROGRAM CODE 1010 1000 0000 0 0 0 0 0 1 0 0 0 0 1 1 DSZ R3 1010 1000 0001 1 1 1 1 1 1 1 0 1 1 1 1 JR -17 1010 1000 0010 1 0 0 1 0 0 1 0 1 1 0 1 MOV R2,13 1010 1001 0011 0 0 0 1 0 0 1 0 0 1 1 0 ADD R2,R6 Note: In the example, register R3 is =0 after decrement, so the instruction DSZ R3 caused the program to skip one instruction on address 1010 1000 0001. Program execution continues at the address 1010 1000 0010. Supplyframe, Inc. 24 OR R0,N Inclusive OR register R0 with 4-bit literal N Syntax: {label} OR Operands: R0 N ∈ 0...15 Operation: (R0) ← (R0) .OR. N, C ← 1 Description: Compute the logical inclusive OR operation of the 4-bit register R0 with the 4-bit literal value N and place the result back into the register R0. Flags aﬀected: Flag C is unconditionally set If result=0000 after operation, set Z. Otherwise, reset Z Encoding: R0, N bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 N N N N The "0000 0101" bits are the OR R0,N opcode The "NNNN" bits are literal N Example: OR R0, 6 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 1 1 0 OPCODE 0000 0101 = OR R0,N Flag C Flag Z Flag V R0 0 1 0 0011 LITERAL N 1 0011 3 R1 R2 C Flag Z Flag V Flag 0 1 1 1 R0 R1 0110 .OR. 6 R3 R2 R3 R4 R5 1 0 0 R4 0111 =7 R5 R6 R6 R7 R7 R8 R8 R9 R9 OUT OUT IN JSR PCL PCM IN Note: This instruction can be used as a direct replacement for the non-existent instruction SET C. In that case, contents of register R0 will be preserved if the literal value is 0000. However, the previous ﬂag Z contents will be lost. PCH PCL PCM PCH Before operation Supplyframe, Inc. JSR After operation 25 AND R0,N Logical AND register R0 with 4-bit literal N Syntax: {label} AND R0, N Operands: R0 N ∈ 0...15 Operation: (R0) ← (R0) .AND. N, C ← 0 Description: Compute the logical inclusive AND operation of the 4-bit register R0 with the 4-bit literal value N and place the result back into the register R0. Flags aﬀected: Flag C is unconditionally reset If result=0000 after operation, set Z. Otherwise, reset Z Encoding: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 N N N N The "0000 0110" bits are the AND R0,N opcode The "NNNN" bits are literal N Example: AND R0, 10 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 1 0 1 0 OPCODE 0000 0110 = AND R0,N Flag C Flag Z Flag V R0 1 1 0 1100 LITERAL N 0 1100 12 R1 R2 C Flag Z Flag V Flag 1 0 0 0 R0 R1 1010 .AND. 10 R3 R2 R3 R4 R5 0 0 0 R4 1000 =8 R5 R6 R6 R7 R7 R8 R8 R9 R9 OUT OUT IN JSR PCL PCM IN Note: This instruction can be used as a direct replacement for the non-existent instruction CLEAR C. In that case, contents of register R0 will be preserved if the literal value is #1111. However, the previous ﬂag Z contents will be lost. PCH PCL PCM PCH Before operation Supplyframe, Inc. JSR After operation 26 XOR R0,N Exclusive OR register R0 with 4-bit literal N Syntax: {label} XOR Operands: R0 N ∈ 0...15 Operation: (R0) ← (R0) .XOR. N, C ← ¬C Description: Compute the logical exclusive OR operation of the 4-bit register (R0) with the 4-bit literal value N and place the result back into the register R0. Flags aﬀected: Flag C is unconditionally toggled (complemented). If result=0000 after operation, set Z. Otherwise, reset Z Encoding: R0, N bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 N N N N The "0000 0111" bits are the XOR R0,N opcode The "NNNN" bits are literal N Example: XOR R0, 3 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 0 0 1 1 OPCODE 0000 0111 = XOR R0,N Flag C Flag Z Flag V R0 LITERAL N 1 1 0 1001 0 0 0 1001 9 R1 R2 Z Flag V Flag 1 0 1 0 R0 R1 0011 .XOR. 3 R3 R2 R3 R4 R5 C Flag R4 1010 = 10 R5 R6 R6 R7 R7 R8 R8 R9 R9 OUT OUT IN JSR PCL IN Note: This instruction can be used as a direct replacement for the non-existent instruction TOGGLE C. In that case, contents of register R0 will be preserved if the literal value is #0000. However, the previous ﬂag Z contents will be lost. JSR PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 27 EXR N Exchange N main registers from the page 0 with the same number of memory locations from the page 14 (page 0x0E) Syntax: {label} EXR N Operands: R0...R15 N ∈ 0...15 (Special case: N=0 means N=16) Operation: (R0)...(RN) ↔ (0xE0)...(0xEN) Description: Exchange N registers from the page 0 with registers from the alternate set in page 14. Special case: if N=0, then 16 registers will be exchanged None. Flags aﬀected: Encoding: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 N N N N The "0000 1000" bits are the EXR N opcode The "NNNN" bits are literal N Example: EXR 10 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 1 0 1 0 OPCODE 0000 10 = EXR N R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 OUT IN JSR PCL PCM PCH 1011 0110 1110 0101 0001 1100 0101 1011 0100 1000 1111 1011 0001 0101 1110 0100 MEMORY LOCATIONS 0XE0-0XEF (PAGE 14) 1110 1001 0010 1110 1100 0000 1101 0111 1101 0011 0001 0100 1101 1011 0011 1010 MEMORY LOCATIONS 0X00-0X0F (R0...R15) 0xE0 R0 0xE1 R1 0xE2 R2 0xE3 R3 0xE4 R4 N MEMORY LOCATIONS 0X00-0X0F (R0...R15) LITERAL N 0xE5 R5 0xE6 R6 0xE7 R7 0xE8 R8 0xE9 R9 0xEA OUT 0xEB IN 0xEC JSR 0xED PCL 0xEE PCM 0xEF PCH Before operation 1110 1001 0010 1110 1100 0000 1101 0111 1101 0011 1111 1011 0001 0101 1110 0100 MEMORY LOCATIONS 0XE0-0XEF (PAGE 14) 1011 0110 1110 0101 0001 1100 0101 1011 0100 1000 0001 0100 1101 1011 0011 1010 After operation Note: Register R0 (data memory location 0x00) is always exchanged with memory location 0xE0, and then, if N≠1, other registers in consecutive order. (Special case: If N=0, then 16 registers will be exchanged.) Supplyframe, Inc. 28 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF BIT RG, M Test bit M in register RG Syntax: {label} BIT Operands: RG ∈ [R0 | R1 | R2 | RS] N ∈ 0 | 1 | 2 | 3 or 0 | 1 | 2 | S Operation: Z ← -<bit> Description: Test bit N in register addressed by RG and update the Z ﬂag. Flags aﬀected: Flag C is not aﬀected. If tested bit is =0, then set Z ﬂag. Otherwise, reset Z. Encoding: RG, M bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 G G M M The "0000 1001" bits are the BIT RG,M opcode The "NNNN" bits are literal N Example: BIT R2, 3 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 1 0 1 1 OPCODE 0000 1001 = BIT RG,M Flag C Flag Z Flag V G 0 1 0 M 0 0 0 C Flag Z Flag V Flag R0 R0 R1 R1 R2 1101 R3 bit 3 2 1 0 1 1 0 1 1 1 0 1 R2 R3 R4 R4 R5 R5 R6 R6 R7 R8 R9 OUT Note: Z ﬂag is set (1) when the tested bit is zero (0), and reset (0) when the tested bit is non-zero (1). That’s why there is an invertor in this logic representation. IN JSR PCL PCM PCH R8 R9 OUT IN Note: If G=0, 1 or 2, then register R0, R1 or R2 is used as the source. If G=3, then register IN is the source. It can be either at the address 0x0B (if WrFlags,1=0) or at the address 0xFB (if WrFlags,1=1). Before operation Supplyframe, Inc. R7 JSR PCL PCM PCH After operation 29 BIT RG,M Test bit M in register RG (CONTINUED) Example 2: bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 1 1 0 0 BIT R3, 0 OPCODE 0000 1001 = BIT RG,M G 0 0 1 Flag C Flag Z Flag V M 0 1 1 Before operation C Flag Z Flag V Flag After operation bit 3 2 1 0 1 1 0 0 Bit IOPOS (WRFLAGS,1) decides if IN register is on the location 0x0B or 0xFB. In this case it is 0, so the location 0x0A is tested for bit state. 00 R0 0 R1 1 R2 2 R3 3 R4 4 R5 5 R6 6 R7 7 R8 8 R9 9 A OUT B 1100 C JSR D PCL E PCM F PCH 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 1 0 0 0 F3 1 0 1 1 FB DATA MEMORY 256 × 4 bits Note: Registers WRFLAGS is described in the manual Special Function Registers Supplyframe, Inc. 30 BSET RG,M Set bit M in register RG Syntax: {label} BSET Operands: RG ∈ [R0 | R1 | R2 | RS] N ∈ 0 | 1 | 2 | 3 or 0 | 1 | 2 | S Operation: <bit> ← 1 Description: Set bit N in register addressed by RG. Flags aﬀected: None. Encoding: RG, M bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 G G M M The "0000 1010" bits are the BSET RG,M opcode The "NNNN" bits are literal N Example: BSET R1, 2 Flag C Flag Z Flag V bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 0 1 1 0 OPCODE 0000 1010 = BSET RG,M G 0 1 0 0 1 0 R0 R1 M C Flag Z Flag V Flag R0 1 1 0 0 R1 1000 R2 R3 bit 3 2 1 0 1 0 0 0 R4 R5 1 R6 R6 R7 R9 R7 1 1 0 0 bit 3 2 1 0 OUT PCL PCM PCH Note: If G=0, 1 or 2, then register R0, R1 or R2 is used as the destination. If G=3, then register IN is the destination. It can be either at the address 0x0A (if WrFlags,1=0) or at the address 0xFA (if WrFlags,1=1). Before operation Supplyframe, Inc. R8 R9 OUT IN JSR R3 R4 R5 R8 R2 IN JSR PCL PCM PCH After operation 31 BSET RG,M Example 2: Set bit M in register RG (CONTINUED) bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 0 1 1 1 1 BSET R3, 3 OPCODE 0000 1010 = BIT RG,M G 1 1 0 Flag C Flag Z Flag V M 1 1 0 C Flag Z Flag V Flag Unchanged Before operation bit 3 2 1 0 0 0 0 0 Before operation 1 1 0 0 0 bit 3 2 1 After operation 0 Bit IOPOS (WRFLAGS,1) decides if the OUT register is on the location 0x0A or 0xFA. In this case it is 1, so the location 0xFA is modiﬁed. 00 R0 0 R1 1 R2 2 R3 3 R4 4 R5 5 R6 6 R7 7 R8 8 R9 9 A 0000 IN B C JSR D PCL E PCM F PCH 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 1 0 1 1 F3 1 0 0 0 FA DATA MEMORY 256 × 4 bits Note: Registers WRFLAGS is described in the manual Special Function Registers Supplyframe, Inc. 32 BCLR RG,M Clear bit M in register RG Syntax: {label} BCLR Operands: RG ∈ [R0 | R1 | R2 | RS] N ∈ 0 | 1 | 2 | 3 or 0 | 1 | 2 | S Operation: <bit> ← 0 Description: Clear bit #N in register addressed by RG. Flags aﬀected: None. Encoding: RG, M bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 G G M M The "0000 1011" bits are the BCLR RG,M opcode The "NNNN" bits are literal N Example: BCLR R0, 1 Flag C Flag Z Flag V R0 bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 0 0 0 1 OPCODE 0000 1011 = BCLR RG,M 0 1 0 C Flag Z Flag V Flag 1 1 0 1 R0 R1 R3 M 0 1 0 1111 R2 G R1 bit 3 2 1 0 1 1 1 1 R2 R3 R4 R4 R5 R5 R6 R6 0 R7 R7 R8 R9 OUT R8 1 1 0 1 bit 3 2 1 0 R9 OUT IN IN JSR JSR PCL PCL PCM PCM PCH PCH Before operation Supplyframe, Inc. After operation 33 BCLR RG,M Example 2: Clear bit M in register RG (CONTINUED) bit 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 1 1 1 1 0 1 BCLR R3, 1 OPCODE 0000 1011 = BCLR RG,M G 1 0 1 Flag C Flag Z Flag V M 1 0 1 C Flag Z Flag V Flag Unchanged Before operation bit 3 2 1 0 1 1 1 0 Before operation 0 1 1 0 0 bit 3 2 1 After operation 0 Bit IOPOS (WRFLAGS,1) decides if the OUT register is on the location 0x0A or 0xFA. In this case it is 0, so the location 0x0A is modiﬁed. 00 R0 0 R1 1 R2 2 R3 3 R4 4 R5 5 R6 6 R7 7 R8 8 R9 9 A 1110 IN B C JSR D PCL E PCM F PCH 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 1 1 0 1 F3 1 1