Manual / Guide · 2022

Supplyframe 4-Bit Processor Badge — User Manual

Author: Supplyframe, Inc.
Year: 2022
Type: Manual / Guide

4-bit processor
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USER MANUAL Revision 4 Nov-02-2022 Supplyframe, Inc. MODE Button Commands COMMAND KEYS ALT DIR Carry Toggle Carry Flag ALT PGM ALT RUN ALT SS Historry Save Load Send Program Memory to Serial Port Load Program Memory from Serial Port Save Program Memory to selected Flash Load Program Memory from selected Flash - Addr Addr + OPCODE OPER X Clock Master Clock source Step OPER Y Opcode Oper X Oper Y Instruction Opcode (bits 11-8) Direct Operand X or Opcode (bits 7-4) Direct Operand Y (bits 3-0) Dimmer level select Baud Rate select Flash portion select for Save / Load Opcode Oper X Oper Y Decrement Increment Execute Enter Instruction Program Program History one Opcode Memory Memory submode instruction (bits 11-8) Address Address Direct Operand X or Opcode (bits 7-4) Direct Operand Y (bits 3-0) Toggle Carry Flag Preset Address Reset set from Program Program Memory Opcode, Memory Address to Operand X Address the last and to 0x000 word used Operand Y Processor Clock select Display Page select Fast Pause User Sync select Opcode Oper X Oper Y Break Run On/Oﬀ Toggle 10× Program Terminate Execution Faster Program Clock and Pause / Execution Resume Sync RUN Program From Program Memory AddrSet Dep + Opcode Oper X Oper Y - Addr Addr + User Sync select Address Write 12-bit set from Decrement Increment word to Program Opcode, Program Program Memory Operand X, Memory Memory Address Address Operand Y and inc PC Instruction Opcode Preset Delete the Reset Page Duplicate the (bits 11-8) Program current word and Pgm current word Memory Mem Address (move all (move all to the last subsequent Address subsequent word used words down) to 0x000 words up) ALT+Both Keys Pressed Supplyframe, Inc. Clear All Memory Processor Clock select Direct Operand X or Opcode (bits 7-4) Display Page select Direct Operand Y (bits 3-0) Gray = ALT key pressed 2 Indicators, buttons and connectors 1. STATUS register, with V (oVerﬂow), Z (Zero) and C (Carry) ﬂags 2. Flag Logic, which generates signals for ﬂags 3. Data Buﬀer/Inverter, switched by Carry Logic (7) and used for Adder/Subtractor 4. Operands, represented and indicated as inputs to ALU unit 5. Arithmetic unit (4-bit Full Adder / Subtractor) as a part of ALU unit 6. Logic unit (4-bit OR / AND / XOR gates) as a part of ALU unit 7. Carry Input Logic (used for Data and Carry Inversion in case of subtraction) 8. Opcode Decoder output (also used as interactive Code Disassembler) 9. Operand X Decoder output (also used as interactive Code Disassembler) 10. Operand Y Decoder output (also used as interactive Code Disassembler) 11. SAO (”Shitty Add-On”) connector, with Ground, +3V and UART Rx/Tx pins 12. I/O connector, with Input and Output ports and PIC MCU Programming pins 13. LED Matrix which displays two pages (2×16 nibbles) of Data Memory 1 2 4 3 6 5 7 8 9 10 11 12 13 T R 1st OPERAND 0 ADD RX,RY ADD R0,N R1 1 2 ADC RX,RY INC RY R2 2 3 SUB RX,RY DEC RY R3 3 4 SBB RX,RY DSZ RY R4 4 5 OR OR R0,N R5 5 6 AND RX,RY AND R0,N R6 6 7 XOR RX,RY XOR R0,N R7 7 8 MOV RX,RY EXR N R8 8 9 MOV RX,N BIT RG,M R9 9 10 MOV [XY],R0 BSET RG,M OUT A 11 MOV R0,[XY] BCLR RG,M IN B 12 MOV [NN],R0 BTG RG,M JSR C PAGE 13 MOV R0,[NN] RRC RY PCL D 0 14 MOV PC,NN RET R0,N PCM E 15 JR SKIP F,M PCH SUM C OR 3 AND 2 1 0 DATA INV XOR CLK IN CLK TMP OUT 2 Z C 1 0 STACK ACCUMULATOR PC 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 MODE ALT DIR CARRY SS HISTORY RUN PAUSE BREAK -- ADDR + ADDR SET PGM LOAD SAVE -- ADDR + FAST CLOCK 15 16 RX,RY NN OPERAND X OPCODE 3 2 1 0 G V Res PAGE F OPERAND Y DATA IN STEP RUN DEP+ 8 ---- 4 - 2 1 + ++++ SYNC 14 1 0 PAGE+1 C OPCODE C S P G 3 2 1 C I 0 R0 Cin C O U T I N 1 R0,N CP Cin ENA 4 V Tx 8-bit opcode Cout ACCU IN GND 0 2nd OPERAND SOURCE V Rx SAO FULL ADDER DEST 3V 17 18 19 8 ---- 4 - DIR: DIM 20 2 1 + ++++ CLOCK 21 8 ---- DIR: BAUD 22 4 - PAGE 23 24 2 1 + ++++ BIN SEL DIR: FLASH 25 14. Three-bit Stack Pointer indicator 15. ALT button, which switches some indicators and buttons to alternate functions 16. MODE button, used to switch between Direct/Single Step/Run/Program mode 17. Command Group of buttons, with Mode-speciﬁc fuctions 18. Program Memory Address pointer (a.k.a. Program Counter, PC) 19. Opcode buttons and indicators (instruction bits 11-8) 20. Symbolic representation and indicators for Accumulator register 21. Page register, determines which page of Data Memory is shown on LED matrix 22. Master Clock signal inverter, used for Master-Slave Flip-Flops triggering 23. Operand X buttons and indicators or Opcode extension (instruction bits 7-4) 24. Operand Y buttons and indicators (instruction bits 3-0) 25. Data In Select button and indicator, switches between Binary and Select mode Supplyframe, Inc. 3 Indicators, buttons and connectors On-Oﬀ Button The only button available at the bottom side is the On-Oﬀ button. Switching On-Oﬀ is possible in every mode, and also when the user’s program is running. In the Oﬀ state, clock signal is halted, the system processor is in Sleep mode and all outputs on the I/O connector (12) are in the highimpedance state. However, there are pull-up resistors on all inputs and pull-down resistors on all outputs. The only exception is the serial Tx output, which does not have not pull-down, but pull-up resistor, as the default level of Tx is high. The resistance of every pull-up and pull-down is 22KΩ. Switching the unit Oﬀ does not aﬀect processor’s registers or contents of memory or program state, so when the unit is turned On again, it will continue the execution as if it wasn’t stopped at all. ALT Button (15) This is the only button that does not initiate the command execution when it is pressed, but it modiﬁes the functions of other buttons and some indicators. It should be used similarly to the Alt button on the computer’s keyboard, which means that it should be pressed prior to the button which function should be modiﬁed. The main Alt-functions of other buttons is printed under the button bar, and it is depended on the mode selected. Here is the function of buttons in the Opcode, Operand X and Operand Y ﬁelds, with the original and modiﬁed function in diﬀerent modes: OPCODE buttons and indicator bar OPERAND X buttons and indicator bar OPERAND Y buttons and indicator bar MODE Original ALT pressed Original ALT pressed Original ALT pressed DIR Opcode Dimmer Operand X Baud rate Operand Y Flash Addr SS Opcode Sync Operand X Clock Operand Y Page Sync RUN PGM Opcode Sync Page Clock Operand X Clock Operand Y Page DATA IN Button and Indicators (25) Used for Data Input Method selection, which aﬀects button groups Opcode, Operand X and Operand Y. The same Data Input Method selection is valid for ALT-functions of the three groups (Sync, Clock, Page, Dimmer, Baud Rate and Flash Address). Every press of the Data In button toggles between the two methods, and the current method is displayed on the BIN/SEL indicators. Here is the description of the two available methods: 1. BINARY Method In the Binary method, every buttons simply toggles the corresponding bit state of the 4-bit selection register, displayed by four indicator above the buttons (Most Signiﬁcant Bit, marked by “8”, is at the left). At the same time, the 16-step indicator bar displays the decoded binary state of the selection register. 2. SELECT Method Buttons “-” and “+” are used to decrement and increment by one the 4-bit binary state of the 4-bit selection register. Buttons “----” and “++++” can be used to decrement and increment the state of the same register by four, which can be used to speed up the selection. Supplyframe, Inc. 4 Indicators, buttons and connectors Preface: Bit coding Before we start with the Opcode and Operand ﬁelds, just a few words about the bit coding ﬁelds inside the instruction word. As the unit is supposed to be programmed directly in a machine language (binary code, ones and zeros), special care was taken to simplify the structure of the instruction codes and pack the bit ﬁelds in 4-bit groups which are easy to perceive and remember. The main code ﬁelds are Opcode and Operands. The typical instruction contains one opcode and a ﬂexible number of operands. Opcode (abbreviated from operation code) is the portion of a machine language instruction that speciﬁes the operation to be performed. In this case, the opcode is always located at the most signiﬁcant bits of the 12-bit instruction word: bits 11-8 or bits 11-4. Operands are values assigned to registers or memory and they are speciﬁed and accessed using more or less complex addressing modes. Here we have instructions which contain one or two operands (but note that there are processors which support more or zero operands). Generally, Operands contain data, and Opcode tells the processor what to do with the data. AFTER EXECUTION: R2=7 INSTRUCTION: 1001 0010 0111 MOV OPCODE R2, 7 OPERAND 1 OPERAND 2 4+2+1=7 8+1=9 SEL MODE: BIN MODE: Buttons Minus (-) and Plus (+) are used to decrement or increment (move up or down) the decoded output. Buttons (----) and (++++) do the same, skipping 4 values at once Decoded state is displayed on the DECODER column Every press on the button ﬂips the LED state: 0 (LED oﬀ) or 1 (LED on) Supplyframe, Inc. Binary state is displayed on the binary row 5 Indicators, buttons and connectors Let’s see how the instruction is organized internally. In this processor, every instruction has the same length, which is 12 bits. Opcode and operands may be located in any part of the instruction code, but in our case, for clarity and ease of programming, the opcode always contains four or eight bits and it is located in the leftmost part of the 12-bit instruction word (highest order bits), and operand or operands are in the rightmost eight or four bits: OPCODE x x x OPERAND X x x x x OPERAND Y x x OPCODE 0 0 0 0 x 0 0 0 x x x x = bit 0 or 1 OPERAND Y x x x OPCODE 0 x x x x RG or F x x x x x x M x x If the opcode is eight bits wide, then the ﬁrst four bits are always 0000. This way of coding gives enough space for a total of 15 instructions with 4-bit opcode (0001-1111), and 16 instructions with 8-bit opcode (00000000-00001111). Please note that there are several instructions (Bit Test/Set/Clear/Toggle and Skip) with the Operand Y ﬁeld split in two 2-bit operands. OPCODE Buttons and Indicators (19) and decoder (8) Buttons in the ﬁeld which is conditionally named Opcode are generally used to preset the four upper (most signiﬁcant) bits of the 12-bit instruction word. The word in binary form is readable on the indicators in the Opcode (19) ﬁeld. The indicator column (8) represents the decoded 4-bit nibble from the Opcode ﬁeld, and it has only one LED in ON state. This column can be conveniently used as the disassembled opcode with the instruction printed next to the LED. If the DATA IN indicator is in the BIN state, Opcode can be entered bit-by-bit, and if it is in the SEL state, the same buttons are used to move the decoded output up/down by one (buttons “-” and “+”) or four places (buttons “----” and “++++”). In Single Step and RUN modes, every modiﬁcation of the Program Memory Address (PC) will automatically read the contents of the instruction and update the Opcode, Operand X and Operand Y indicators. You can modify it using buttons, end even execute the new state in SS mode (by pressing button STEP), but it will not aﬀect the contents of the Program Memory. The only way to alter the contents of the Program Memory is to press the DEPosit button in PGM mode. Supplyframe, Inc. 6 Indicators, buttons and connectors OPERAND X Buttons and Indicators (23) and decoder (9) Buttons and indicators in the OPERAND X group are used to preset the central nibble (bits 74) of the instruction. If the Opcode ﬁeld contains bits 0000, Operand X ﬁeld does not represent the operand anymore, but the extension of the Opcode ﬁeld. The word in binary form is readable on the indicators in the Operand X (23) ﬁeld. The indicator column (9) represents the decoded 4-bit nibble from the Operand X ﬁeld, and it has only one LED in ON state. This column can be conveniently used as the disassembled opcode, but the special care should be taken if the Opcode ﬁeld contains 0000, as the instruction printed next to the LED is valid only in that case. In all other cases, the decoded output should be treated as the register name printed next to the LED matrix ﬁeld (Data Memory). If the DATA IN indicator is at the BIN state, Operand X can be entered bit-by-bit, and if it is in the SEL state, the same buttons are used to move the decoded output up/down by one (buttons “-” and “+”) or four places (buttons “----” and “++++”). In Single Step and PGM modes, every modiﬁcation of the Program Memory Address (PC) will automatically read the contents of the instruction and update the Opcode, Operand X and Operand Y indicators. You can modify it using buttons, end even execute the new state in SS mode (by pressing button STEP), but it will not aﬀect the contents of the Program Memory unless you press the DEPosit button in PGM mode. Column (9) contains one extra indicator, which is in the instruction EXR R0,N ﬁeld. This instruction exchanges a group of General Purpose and Special Purpose registers from the Page 0 with the equivalent number of nibbles in the Page 14 of Data Memory, and the indicator is ﬂipped every time when the instruction is executed. So the indicator should be ON only when register contents are exchanged between Page 0 and Page 14 and OFF when they are ﬂipped back to their original positions. That couls help keeping track of program execution. In Single Step and RUN modes, the function of Operand X buttons and indicators is modiﬁed when the ALT button is depressed. In that case, Clock register is accessible instead of Operand X register. Clock register is used to adjust the processor speed. OPERAND Y Buttons and Indicators (24) and decoder (10) Buttons and indicators in the OPERAND Y group are used to preset the lower nibble (bits 30) of the instruction. The word in binary form is readable on the indicators in the Operand Y (24) ﬁeld. The indicator column (10) represents the decoded 4-bit nibble from the Operand Y ﬁeld, and it has only one LED in ON state. This column can be conveniently used as the disassembled opcode, and it is valid for most instructions, but not for instructions Bit Test/Set/Clear/Toggle and Skip, which split the ﬁeld which we named as Operand Y in two 2-bit operands. For these instructions, decoding should be performed manually. If the DATA IN indicator is at the BIN state, Operand Y can be entered bit-by-bit, and if it is in the SEL state, the same buttons are used to move the decoded output up/down by one (buttons “-” and “+”) or four places (buttons “----” and “++++”). In Single Step and PGM modes, every modiﬁcation of the Program Memory Address (PC) will automatically cause reading of the contents of the new instruction and update the Opcode, Operand X and Operand Y indicators. You can modify it using buttons, end even execute the new state in SS mode (by pressing button STEP), but it will not aﬀect the contents of the Program Memory unless you press the DEPosit button in PGM mode. In Single Step and RUN modes, the function of Operand Y buttons and indicators is modiﬁed when the ALT button is depressed. In that case, Page register is accessible instead of Operand Y register. Supplyframe, Inc. 7 Indicators, buttons and connectors LED Matrix (Data Memory) (13) and Page indicator (21) Data Memory display is visually organized as 16×8 matrix, but it is functionally divided in two 16×4 displays. The right 16×4 half displays the contents of one Data Memory page deﬁned by the state of the Page register (21), and the left half is for the next one (Page+1). The whole Data Memory contains 256 nibbles, which gives a total of 16 pages, and if the right half displays the last page (Page 15), then the left half is wrapped to the beginning of the address space as Page 0. This enables watching both General Function Registers (on Page 0) and Special Function Registers (Page 15) at the same time. Bit 3 2 1 0 3 2 1 0 Page × 16 (Page+1) × 16 IN THIS EXAMPLE Version Revision Year Month Day 1 5 20 7 12 Bootloader Checksum 0xC651 Firmware Checksum 0x3A9E Page Page+1 (Page+1) × 16 + 15 Page × 16 + 15 Data Memory display (13) is disabled in DIRect and PGM modes, but in DIRect mode it has the special function when the ALT button is pressed. Then it displays the occupancy of 16 Flash Memory blocks, which can help in Flash Memory organization and navigation. Also, after the Master Reset, Data Memory Display in DIRect mode (which is default after Reset) shows the Version/Revision/Year/Month/Day numbers or the ﬁrmware release at the ﬁrst ﬁve rows of the LED Matrix. In the middle of the matrix (rows 10 and 11) there is the Checksum of Program Memory for the Bootloader Segment, and, on the two bottom rows, the Checksum for the General Segment (main ﬁrmware). Master Reset is possible only after the batteries are disconnected and then reconnected, or when pins G (Ground) and Res (Reset) of the I/O Connector are shortened externally. After any button is pressed, this data is cleared from the display. Note that Master Reset also clears all Program and Data Memory, but not the contents saved in the internal Flash. Data Memory display can be disabled under the program control, if bit 2 (MatrixOﬀ) in the register WrFlags (Address 0xF3) is set. If bit 3 (LedsOﬀ) in the register WrFlags (Address 0xF3) is set, all other LEDs will be disabled, only the LED CLK or INVERSE CLK (on the schematic drawing) will still be ON. These LEDs are the indicator that the unit is in operation (or, if they are alternatively blinking, that it is running), and they can not be disabled. Page is the 4-bit register which is accessible to the user’s program in the Special Function Register (SFR) group, in the data memory address 0xF0. In modes SS and RUN it can be easily preset manually, when the ALT button is depressed and the Operand Y buttons are used for Page contents adjusting. At every program Run, the Page register is reset to 0000. Mode Single Step (SS) has its own Page register, so if some value was preset in SS mode, it will be kept and restored at every reentry to the SS mode. Supplyframe, Inc. 8 Indicators, buttons and connectors 1st and 2nd OPERAND (Input to ALU unit) (4) This is the ﬁrst ﬁeld of the ALU/Accumulator data ﬂow, which is in the core of the processor. The data indicated in this ﬁeld actually do not exist as registers, but only displays the input states to the ALU, and thus makes it easier to follow the process. Please note the diﬀerence between these pairs of terms: “Operand X” - “Operand Y”, “1st Operand” - “2nd Operand”, and “Source” - “Destination” In many cases these pairs of terms will mean the same, but there are also cases when there is the diﬀerence. Operands X and Y are simply operands which are deﬁned in X and Y ﬁelds on the panel, and that’s all. At the other hand, 1st and 2nd operands are just deﬁned by the order of appearance, and Source and Destination are exactly what these words mean. There are diﬀerent rules for diﬀerent processors, but here the most popular rule is applied. If there are two operands, then the ﬁrst one is always the destination (sometimes it's also the source), and the second one is always the source. So if the instruction is: ADD RX, RY that means “Add Arithmetically contents of Register Y to the contents of Register X and write the result in Register X”. Some instructions have only one operand. In general case, it is source and destination at the same time. For instance: INC RY means “Increment the value of Register Y by one and write the result in Register Y”. It’s obvious that there was an invisible source, which is the literal “1”, added to the Register Y. Sometimes the destination is hidden as the operand, and you have to know the operation deﬁned by the Opcode, to know where the result is stored: BIT R2, 3 This operation tests bit 3 in register R2, so it’s the single bit source, but where is the destination? In this instruction, it is the single bit destination, Flag Z. To make it more complicated, if bit 3 in register R2 is 0, the resulting ﬂag Z will be 1, and vice versa. But it makes more sense when we know that Z (Zero) Flag is set (1) when the result of the operation is Zero (0). It is clear that it is not easy to deﬁne the operands precisely, so the representation of input signal to the ALU will sometimes be inaccurate. Also, captions “DEST” and “SOURCE” next to the indicators are only roughly informative. 4-bit Full Adder / Subtractor (5) Arithmetic unit performs adding and subtracting operations either with unsigned positive, or Two’s complement signed (either positive or negative) binary numbers. “Full” Adder means that it not only adds bits, but also processes Carry (C) bit. So every bit stage has three inputs (A, B and Carry from the previous stage) and two outputs (Sum and Carry to the next stage). The Carry input of the LSB (Least Signiﬁcant Bit) is the global Carry input to the adder, and the output from the MSB (Most Signiﬁcant Bit) is the global Carry output. Subtracting is actually adding of negative value, so the source operand is inverted. To make it negative in 2’s complement form, it should be also incremented by one, but the inverse Carry logic (which is named Borrow) in subtraction process compensates this and always gives the correct result, even without adding. If there is the Borrow condition (no Carry), then the resulting -1 diﬀerence (caused by non-adding 1 at negation) automatically adds Borrow (-1) to the result, and No Borrow (Carry set) adds 1 and again compensates 2’s complement negation. Adder/Subtractor is used not only for Add and Subtract instructions (with or without Carry or Borrow), but also for CP (Compare) instruction. Compare is actually same as Subtract, but the result is not written anywhere but lost, only the ﬂags are preserved. Supplyframe, Inc. 9 Indicators, buttons and connectors It’s amazing to learn about the theory of operation of the binary adder/subtractor. Two’s complement binary math sometimes looks like magic, when everything turns simple with inverting and negating binary numbers and processing them always in the same adder/subtractor hardware. The Carry logic not only “works” for adding and subtracting, but also for signed numbers processing in the same hardware. IN B 3 1st OPERAND 2nd OPERAND IN A 3 IN B 2 IN A 2 IN B 1 IN A 1 IN B 0 IN A 0 Overﬂow Carry In Carry Out SUM 3 SUM 2 SUM 1 SUM 0 In a few words, signed numbers in the 2’s complement math are represented so that MSB (leftmost bit) is the sign (”0” for “+”, “1” for “-”), and all other bits follow the 2’complement rule (inverted bits plus 1). So there is one bit less for the number representation, as the range for the 4bit signed number is -8 to +7 (for the 8-bit number, it would be -128 to +127), but everything else is quite simple: adding and subtracting can be performed in the same adder/subtractor hardware! Adding and subtracting of longer (unsigned positive or signed negative or positive) numbers is performed in serial manner, using Carry/Borrow bit for linking. This is the example how to add or subtract two 16-bit numbers, wether they are unsigned positive or signed negative or positive. If one number is in registers R0, R1, R2 and R3, and the another one in R4, R5, R6 and R7, after this addition (or subtraction) the result will be in R0, R1, R2 and R3: Addition: ADD R0, R4 ADC R1, R5 ADC R2, R6 ADC R3, R7 Subtraction: SUB R0, R4 SBB R1, R5 SBB R2, R6 SBB R3, R7 Note that the ﬁrst operation is without Carry (or Borrow), and all others are with Carry (or Borrow). This method can be used to add or subtract numbers of any length. The example uses the Little Endian notation (Least Signiﬁcant nibbles are written in the lower address of memory or register ﬁle). The principle is the same for Big Endian notation (Most Signiﬁcant nibbles on low addresses, Least Signiﬁcant on top), but the order of registers would be reversed (ADD R3, R7, then ADC R2, R6, and so on). Lowest bits are always processed ﬁrst. The same technique is applicable for adding or subtracting of signed numbers of any length. The rule is that there is only one Sign bit for the number of any length, always at the MSB location of the Most Signiﬁcant nibble. For the unsigned binary numbers, the global Carry (or Borrow) bit for the result is available after the last ADC (or SBB) instruction. If the Carry Flag is set, that means that the addition has overﬂowed and the result can’t ﬁt the register width. For subtraction, the outcome is reversed: No Carry (which means Borrow Set) means that the result has overﬂowed (the correct word here is Underﬂowed) and thus not usable. This was valid for unsigned numbers, but for signed numbers Carry Flag outcome has no meaning, but the V (Overﬂow) Flag is used instead. So if V Flag is set, the result has overﬂowed or underﬂowed (can not be represented in the existing register) and it is not usable. V Flag has no meaning for the unsigned numbers, so it is not frequently used. That’s why it is not present as a condition in the SKIP instruction, but it is available and can be tested (using the instruction BIT RG, M) in the SFR (Special Function Register) named RdFlags, bit 1. The Special Function Register RdFlags is at the Data Memory address 0xF3. Overﬂow Flag (V) is generated in the adder/subtractor hardware circuit in a very simple way: if the Carry Input to the last Adder bit and the Carry Output from the same adder bit are diﬀerent, the Overﬂow Flag is set, and that’s all. So the single XOR circuit does the whole task, and it is just another example of the simplicity and beauty of the adder/subtractor circuit. Supplyframe, Inc. 10 Indicators, buttons and connectors Carry Input Logic (7) and Data Buﬀer/Inverter (3) This is the simple logic circuit which inverts Carry logic level and Data Bus signals for subtraction, and leaves them unchanged (true logic) for addition. Also, it switches oﬀ the Carry input signal (forces it to Low for addition, or High for subtraction) in the operations which do not process Carry input signal (ADD, SUB and CP). Carry In Enable D3 D2 D1 D0 ADC SUB, CP Adder Carry In SBB D3 D2 D1 D0 Previous Carry D3 D2 D1 D0 Adder Carry In D3 D2 D1 D0 D3 D2 D1 D0 Adder Carry In D3 D2 D1 Carry In Invert (Carry In Invert) = 1 (Carry In Invert) = 0 D0 Logic XOR circuit, which is at the input of the Adder and which generates Cin signal, simply inverts the Carry signal if the Carry In Invert =1, and serves as a single buﬀer (which does not modify the signal level) if Carry In Invert =0. The same is valid for all DATA signals in the internal DATA BUS (there is only one representation of the Data Bus XOR circuit on the panel schematics). So both Carry and Data are inverted if the instruction involves Subtraction. Logic unit (4-bit OR / AND / XOR gates) (6) This is the second part of the ALU unit, where logic instructions are performed. Its structure is quite straightforward, but several facts should be noted before we ﬁnish the description of ALU. Due to the lack of space on the panel, the schematic of ALU circuit is simpliﬁed. One of the circuits that is missing is the complex part of the instruction decoder, which selects not only the result from the adder or some of logic outputs (OR, AND or XOR), but also the data path from Data Memory to the Accumulator inputs, the I/O data path, SFR logic and so on. The vast majority of the circuits are not represented, simply because it would, even in the simplest possible project, require the panel to be the size of the average table surface, with thousands of gates and many indicators. Also, the ALU circuit is not optimized, but drawn so that it is clear and straightforward. The real ALU circuit in the microprocessor looks much less familiar and hard to follow and understand at the ﬁrst sight, as the number of gates is minimized. One more thing which is diﬀerent in modern processors is the Carry Generator logic. This “serial” approach works correctly, but it slows down the operation of the processor, due to the propagation delays on the long path, through many gates from the Carry Input to the Carry Output. Note that there is also (but not represented here) the Fast Carry Generator, which works in parallel mode and thus requires more gates, but has much lower propagation delay. Supplyframe, Inc. 11 Indicators, buttons and connectors Accumulator (20) and Master Clock Signal Inverter (22) The ﬁrst thing that should be noted is that there is not one, but 16 Accumulators in this processor, and they are named as Registers R0-R15. So it’s good to imagine them as 16 layers of the accumulator schematics, and only one is selected and visible, depended which register is the destination one. Please note that some instructions need no accumulator, as the destination may be the Data Memory nibble, Program Counter, or even a single bit (Flag) in the Status Register. The accumulator contains a series of four Flip-Flops, not a simple ones, but Master-Slave Edge-Triggered D Flip-Flops. MASTER LOCKED SLAVE Slave Out Data In Data Out LOCKED LOCKED Master Out PHASE 1 Clock Clock (Enable High) PHASE 2 In the ﬁrst phase of the Clock signal on the Master-Slave Edge-Triggered D Flip-Flop schematics, when the Clock signal is High (in Single Step or Direct mode, it’s when the button Step or Clock is pressed), the ﬁrst Flip-Flop is in transparent state (unlocked). When the Clock logic level is changed to Low, the ﬁrst Flip-Flop (the Master one) latches the Data logic level and the second (Slave) Flip-Flop is in transparent state. This two-fold latching solves the problem of circular self-triggering when the same register serves as the source and the destination at the same time, as one of Flip-Flops is always latched. The Master Flip-Flop output can change its state only when the Clock signal is high, but the Slave output can be changed only in the moment of the falling edge of the Clock signal. (Note: ignore Enable signal for now.) Of course the best way would be to have the full schematics with 16 Accumulators, but the available space on the panel allows only one. It must be switched with every new instruction, so that it displays the logic states of the register or memory location which is the current destination, and it may cause the unexpected switching of the output logic states of the Accumulator. For instance, when the button Step is ﬁrst depressed in Single Step mode, the input logic states are transferred to the Temporary Outputs (outputs of Master Flip-Flops), but when the button is released, the same logic states would normally appear on Accumulator Outputs. However, the new instruction is read from the Program Memory, possibly with the new destination, and now the Accumulator represents the new register. That's why its logic states were unexpectedly changed. This does not happen in Direct mode, at least in most cases, when the destination stays the same, so it is much easier to follow the data ﬂow in the Direct mode. Supplyframe, Inc. 12 Indicators, buttons and connectors STATUS register (1) and FLAG logic (2) Status register, which contains Overﬂow, Zero and Carry ﬂags, is probably the simplest, but among the most important parts of processor’s hardware. Flags are kind of decision-makers in the program ﬂow, and the Carry Flag is sometimes called the 1-bit Accumulator. Flags are propagated through the Status Register in a similar way as Data Bits are propagated through the Accumulator: there are three Master-Slave Edge-Triggered D FlipFlops, which are triggered with the same Clock signal and at the same time as the Accumulator Flip-Flops. The Status Flip-Flops are not represented on the panel schematics in order to save space, but they are the same and triggered by the same Clock and Inverse Clock signals. This is a good moment to say that there is the logic circuit which decides if the Flip-Flop will be clocked or not. Actually, the Instruction Decoder decides about that: some instructions have to keep the existing contents of the Accumulator, or individual Flags. Only when the Accumulator (to be more speciﬁc, the addressed register) is the destination of the operation, its contents should be clocked. If the current instruction does not aﬀect Flags or Accumulator contents, the instruction decoder pulls the Enable signal low in the corresponding Flip-Flop(s), and thus locks the Flip-Flop state. The same is valid for every ﬂag individually, as some instructions do not aﬀect some ﬂags, and they should be preserved safely in the Flip-Flop. The additional logic inputs, which disable the Flip-Flop clocking, is represented on the following schematics. There are the same Latch Enable inputs on the Accumulator Flip-Flops, as the contents of the Accumulator should be preserved in the case when it is not the destination (bit oriented instructions, program branching or compare instructions). Note that Enable inputs are not drawn on the simpliﬁed panel drawing. MASTER SLAVE Data In Data Out Enable Clock We have seen how simply the Overﬂow Flag is generated: a single XOR logic circuit detects the single-bit logic equality at the Carry Input and Carry Output signals of the last stage of the Adder. Zero Flag logic is also simple, as it only tests the Accumulator input for Zero. There is only one exception: instruction BIT RG, M sets or resets the Zero Flag depended on the tested bit state. Note that Zero condition always sets Zero Flag to Non-Zero, and Non-Zero condition resets it to Zero. This is valid not only for BIT RG, M instruction, but also in every other case. If the result is Zero (all bits are 0000), the Zero Flag will be set (1), and if one or more bits in the result are set (1), the Zero Flag will be reset (0). In a few words, Zero Flag = 1 means Zero, and Zero Flag = 0 means Non-Zero. Carry Flag can be a result of arithmetical or bitwise rotation. It can also be unconditionally set by the instruction OR R0,N, reset (AND R0,N) or toggled (XOR R0,N). The drawing on the following page, which represents Carry signal ﬂow, is valid for ADD/ADC/SUB/SBB instructions (including CP also, which is the same as SUB, only without storing the result), but a similar ﬂow could be drawn for RRC (Rotate Right Through Carry) also. Carry Flag has a complex behavior, so it is represented in as much as nine indicators on the panel schematics. Please look the following page. Supplyframe, Inc. 13 Indicators, buttons and connectors 8 9 7 5 6 T R 1st OPERAND 0 ADD RX,RY ADD R0,N R1 1 2 ADC RX,RY INC RY R2 2 3 SUB RX,RY DEC RY R3 3 4 SBB RX,RY DSZ RY R4 4 5 OR OR R0,N R5 5 6 AND RX,RY AND R0,N R6 6 7 XOR RX,RY XOR R0,N R7 7 8 MOV RX,RY EXR N R8 8 9 MOV RX,N BIT RG,M R9 9 10 MOV [XY],R0 BSET RG,M OUT A 11 MOV R0,[XY] BCLR RG,M IN B 12 MOV [NN],R0 BTG RG,M JSR C PAGE 13 MOV R0,[NN] RRC RY PCL D 0 14 MOV PC,NN RET R0,N PCM E 15 JR SKIP F,M PCH SUM C OR 3 AND 2 1 0 DATA INV XOR 1 2 3 CLK IN CLK TMP OUT V 2 4 Z C ACCUMULATOR PC 11 1 0 STACK 10 9 8 7 6 5 4 3 2 1 0 3 2 1 MODE DIR ALT SS CARRY HISTORY RUN FAST PGM ADDR SET LOAD SAVE -- ADDR + PAUSE BREAK -- ADDR + CLOCK 1 0 3 2 1 0 G V Res PAGE+1 C OPCODE C S P G 3 2 1 C I 0 R0 Cin C O U T I N 1 R0,N CP Cout ACCU IN Tx 8-bit opcode Cin ENA 4 S GND 0 2nd OPERAND SOURCE V Rx SAO FULL ADDER DEST 3V RX,RY NN OPERAND X OPCODE PAGE F OPERAND Y DATA IN STEP 8 RUN ---- DEP+ 4 - SYNC 2 1 + ++++ 8 4 ---- - DIR: DIM 2 1 + ++++ CLOCK 8 ---- DIR: BAUD 4 - PAGE 2 1 + ++++ BIN SEL DIR: FLASH Nine indicators represent the same ﬂag, and yet every one has the diﬀerent meaning. After the selector S, which is under the control of the instruction decoder, the 1-bit content of the Carry Flag is fed to the input of Carry Flip-Flop (1) in the Status register. If the instruction is supposed to aﬀect the Carry Flag, the Clock signal will ﬁrst load the content to the TMP point (2) (Master FlipFlop output), and then to the Carry Output (3) of the Status register. At the same moment, the Carry Flag LED (4), which is in the Command Buttons ﬁeld, fetches the same state. This indicator is not a part of the typical processor, but it is included in this model as it allows the user to modify the Carry Flag state manually, for experimenting. So you can watch interactively how Carry Flag aﬀects the Adder states. After passing through the simple logic, which inverts Carry Flag in the case of subtraction and turns it oﬀ if no Carry input is needed, there are Intermedial Carry Flags (6), (7), (8) between the Adder stages, before the ﬁnal Carry (9) is generated. In the case of the RRC Y instruction, the data ﬂow of the Carry Flag is not represented here in detail, but there is the D0 (Data 0) signal extracted from the internal Data Bus, which is fed to the rightmost contact of the Selector S. So the D0 logic state is driven to the Carry Flag, and the rest of the data ﬂow is represented on the following schematics diagram: RRC Y ACCUMULATOR Adder C out 0 1 C D0 Carry OPCODE SLAVE + MASTER CARRY D3 D2 D1 D0 C Clock Supplyframe, Inc. 14 Indicators, buttons and connectors Stack Pointer (SP) (14) This three-bit register is used to address the Data Memory where the Program Counter (PC) will be stored during the execution of the subroutine (writing to JSR General Purpose Register), and restored back to Program Counter at the execution of RETURN (RET R0,N instruction). Program Counter contains 12 bits (3 Data Memory locations), so one Stack position requires 3 nibbles for storing. When the subroutine is called (when the program writes a nibble in JSR General Purpose Register, on location 0x0C), PC is stored at the Data Memory location 0x10+3×[SP] (loworder address nibble ﬁrst). Then the SP register is incremented by one, and JSR, PCM and PCH registers are copied to the PC (JSR is the low-order address nibble). When the Return from subroutine (instruction RET R0,N) is executed, literal N is loaded to the register R0, then the SP is decremented by one, and contents of Data Memory from the three locations (the ﬁrst one is 0x10+3×[SP]) is written back to the PC. Note that both SP and PC registers are not available directly to the user’s program. A total of 5 levels of Stack Pointer can be used in the program, which means that only the ﬁrst 15 Data Memory locations from the Page 1 will be used for the Stack storage. If the SP overﬂows to 110 (decimal 6), which will happen if subroutines are called 6 times without executing RET R0,N, program execution will be halted and the Error condition will be indicated, so that the Stack indicator will blink at the value 110 (which is the attempted value when the error occurred). The Error condition should be cleared by pressing any key (the command assigned to the key will not be executed). If more Returns (instructions RET R0,N) are executed than Calls (writing to the register JSR), register SP will be in the underﬂow condition. Program execution will be halted and the Error condition will be indicated, so that the Stack indicator will blink at the value 111 (decimal -1 in signed notation). All register indicators and Data Memory matrix are still active, so the user can see the PC Address and other conditions under whic